cpe631isa - CPE 631: Instruction Set Principles and...

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CPE 631: Instruction Set Principles and Examples Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic, milenka@ece.uah.edu http://www.ece.uah.edu/~milenka
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2 AM L a CA S A Outline What is Instruction Set Architecture? Classifying ISA Elements of ISA Programming Registers Type and Size of Operands Addressing Modes Types of Operations Instruction Encoding Role of Compilers
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3 AM L a CA S A Shift in Applications Area Desktop Computing – emphasizes performance of programs with integer and floating point data types; little regard for program size or processor power Servers - used primarily for database, file server, and web applications; FP performance is much less important for performance than integers and strings Embedded applications value cost and power, so code size is important because less memory is both cheaper and lower power DSPs and media processors , which can be used in embedded applications, emphasize real-time performance and often deal with infinite, continuous streams of data Architects of these machines traditionally identify a small number of key kernels that are critical to success, and hence are often supplied by the manufacturer.
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4 AM L a CA S A What is ISA? Instruction Set Architecture – the computer visible to the assembler language programmer or compiler writer ISA includes Programming Registers Operand Access Type and Size of Operands Instruction Set Addressing Modes Instruction Encoding
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5 AM L a CA S A Classifying ISA Stack Architectures - operands are implicitly on the top of the stack Accumulator Architectures - one operand is implicitly accumulator General-Purpose Register Architectures - only explicit operands, either registers or memory locations register-memory: access memory as part of any instruction register-register: access memory only with load and store instructions
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6 AM L a CA S A Classifying ISA (cont’d) For classes: Stack, Accumulator, Register-Memory, Load-store (or Register-Register) TOS Processor Memory ... ... Stack Processor Memory ... ... Accumulator Processor Memory ... ... Register-Memory Processor Memory ... ... Register-Register
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7 AM L a CA S A Example: Code Sequence for C = A+B Stack Accumulator Register-Memory Load-store Push A Push B Add Pop C Load A Add B Store C Load R1,A Add R3,R1,B Store C, R3 Load R1,A Load R2,B Add R3,R1,R2 Store C,R3 4 instr. 3 mem. op. 3 instr. 3 mem. op. 3 instr. 3 mem. op. 4 instr. 3 mem. op.
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AM L a CA S A Development of ISA Early computers used stack or accumulator architectures accumulator architecture easy to build stack architecture closely matches expression evaluation algorithms (without optimisations!) GPR architectures dominate from 1975 registers are faster than memory registers are easier for a compiler to use hold variables memory traffic is reduced, and the program speedups
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cpe631isa - CPE 631: Instruction Set Principles and...

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