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cpe631memory - CPE 631 Memory Electrical and Computer...

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CPE 631 Memory Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic [email protected] http://www.ece.uah.edu/~milenka
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2 AM L a CA S A Virtual Memory: Topics Why virtual memory? Virtual to physical address translation Page Table Translation Lookaside Buffer (TLB)
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3 AM L a CA S A Another View of Memory Hierarchy Regs L2 Cache Memory Disk Tape Instructions, Operands Blocks Pages Files Upper Level Lower Level Faster Larger Cache Blocks Thus far { Next: Virtual Memory {
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4 AM L a CA S A Why Virtual Memory? Today computers run multiple processes, each with its own address space Too expensive to dedicate a full-address-space worth of memory for each process Principle of Locality allows caches to offer speed of cache memory with size of DRAM memory DRAM can act as a “cache” for secondary storage (disk) Virtual Memory Virtual memory – divides physical memory into blocks and allocate them to different processes
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5 AM L a CA S A Virtual Memory Motivation Historically virtual memory was invented when programs became too large for physical memory Allows OS to share memory and protect programs from each other (main reason today) Provides illusion of very large memory sum of the memory of many jobs greater than physical memory allows each job to exceed the size of physical mem. Allows available physical memory to be very well utilized Exploits memory hierarchy to keep average access time low
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6 AM L a CA S A Mapping Virtual to Physical Memory Program with 4 pages (A, B, C, D) Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”) Physical Memory Virtual Memory A B C D D A B C 0 4 KB 8 KB 12 KB 0 4 KB 8 KB 12 KB 16 KB 20 KB 24 KB 28 KB Disk
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7 AM L a CA S A Virtual Memory Terminology Virtual Address address used by the programmer; CPU produces virtual addresses Virtual Address Space collection of such addresses Memory (Physical or Real) Address address of word in physical memory Memory mapping or address translation process of virtual to physical address translation More on terminology Page or Segment Block Page Fault or Address Fault Miss
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8 AM L a CA S A Comparing the 2 levels of hierarchy Parameter L1 Cache Virtual Memory Block/Page 16B – 128B 4KB – 64KB Hit time 1 – 3 cc 50 – 150 cc Miss Penalty (Access time) (Transfer time) 8 – 150 cc 6 – 130 cc 2 – 20 cc 1M – 10M cc (Page Fault ) 800K – 8M cc 200K – 2M cc Miss Rate 0.1 – 10% 0.00001 – 0.001% Placement: DM or N-way SA Fully associative (OS allows pages to be placed anywhere in main memory) Address Mapping 25-45 bit physical address to 14-20 bit cache address 32-64 bit virtual address to 25- 45 bit physical address Replacement: LRU or Random (HW cntr.) LRU (SW controlled) Write Policy WB or WT WB
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9 AM L a CA S A Paging vs. Segmentation Two classes of virtual memory Pages - fixed size blocks (4KB – 64KB) Segments - variable size blocks
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