cpe631review - CPE 631 Review: Pipelining Electrical and...

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CPE 631 Review: Pipelining Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic, [email protected] http://www.ece.uah.edu/~milenka
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2 AM L a CA S A Outline Pipelined Execution 5 Steps in MIPS Datapath Pipeline Hazards Structural Data Control
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3 AM L a CA S A Laundry Example (by David Patterson) Four loads of clothes: A, B, C, D Task: each one to wash, dry, and fold Resources Washer takes 30 minutes Dryer takes 40 minutes “Folder” takes 20 minutes A B C D
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4 AM L a CA S A Sequential Laundry Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? A B C D 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time
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5 AM L a CA S A Pipelined Laundry Pipelined laundry takes 3.5 hours for 4 loads A B C D 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time 30 40 40 40 40 20
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6 AM L a CA S A Pipelining Lessons Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate is limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to “ fill ” pipeline and time to “ drain ” reduce speedup A B C D 6 PM 7 8 9 T a s k O r d e r Time 30 40 40 40 40 20
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7 AM L a CA S A Computer Pipelines Execute billions of instructions, so throughput is what matters What is desirable in instruction sets for pipelining? Variable length instructions vs. all instructions same length? Memory operands part of any operation vs. memory operands only in loads or stores? Register operand many places in instruction format vs. registers located in same place?
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8 AM L a CA S A A "Typical" RISC Registers 32 64-bit general-purpose (integer) registers (R0-R31) 32 64-bit floating-point registers (F0-F31) Data types 8-bit bytes, 16-bit half-words, 32-bit words, 64-bit double words for integer data 32-bit single- or 64-bit double-precision numbers Addressing Modes for MIPS Data Transfers Load-store architecture: Immediate, Displacement Memory is byte addressable with a 64-bit address Mode bit to select Big Endian or Little Endian
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9 AM L a CA S A MIPS64 Instruction Formats Op 31 26 0 15 16 20 21 25 Rs Rt immediate Op 31 26 0 25 Op 31 26 0 15 16 20 21 25 Rs Rt address Rd funct Register-Register 5 6 10 11 Register-Immediate Jump / Call shamt Op 31 26 0 15 16 20 21 25 Fmt Ft Fs funct 5 6 10 11 Fd Floating-point (FR) Op 31 26 0 15 16 20 21 25 Fmt Ft immediate Floating-point (FI)
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10 AM L a CA S A MIPS64 Instructions MIPS Operations (See Appendix B, Figure B.26) Data Transfers (LB, LBU, SB, LH, LHU, SH, LW, LWU, SW, LD, SD, L.S, L.D, S.S, S.D, MFCO, MTCO, MOV.S, MOV.D, MFC1, MTC1) Arithmetic/Logical (DADD, DADDI, DADDU, DADDIU, DSUB, DSUBU, DMUL, DMULU, DDIV, DDIVU, MADD, AND, ANDI,
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This note was uploaded on 12/13/2011 for the course CPE 631 taught by Professor Staff during the Spring '10 term at University of Alabama - Huntsville.

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cpe631review - CPE 631 Review: Pipelining Electrical and...

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