cs61c_fa10_f - Fall 2010 CS61C Final Your Name: _ Your TA:...

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1 Fall 2010 CS61C Final Your Name: ______________________________________________________________ Your TA: Andrew Michael Conor Charles Login: cs61c-___ This exam is worth 186 points, or about 20% of your total course grade. The exam contains 10 questions. This booklet contains 14 numbered pages including the cover page, plus the 2 pages for the green card. Put all answers on these pages, please; don't hand in stray pieces of paper. Question Points (Minutes) Score 1. Justified 30 points (15 minutes) 2. Virtuosity 14 (7) 3. Mo’ Cache, Mo’ Problems 24 (12) 4. My Secret Cache 34 (17) 5. Heaven’s Gate 8 (4) 6. Off the Map 20 (10) 7. Pay It Forward 12 (6) 8. Bigger, Stronger, Faster 10 (5) 9. Altered States 10 (5) 10. Three’s Company 24 (12) Total 186 points (93 minutes)
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2 1. Justified . True or False with Justification Circle whether each statement in questions a) to g) is True or False, and give a one sentence justification . We reserve the right to dock points for long-winded answers. Be concise! If you feel like you can give a clear justification in just one word, please do! a. Designing a processor with dynamic multiple issue places extra burden on the compiler author to ensure the correctness of emitted code. TRUE / FALSE Justification: b. As a result of hitting the Power Wall, Moore ʼ s Law no longer holds. TRUE / FALSE Justification: c. Increasing the depth of a pipeline tends to increase performance primarily by decreasing the amount of time it takes on average to execute a particular instruction. TRUE / FALSE Justification: d. In a single-cycle MIPS CPU during the execution of a jump instruction, the adder block inside the ALU always computes the sum of its inputs. TRUE / FALSE Justification: e. After enough time, a circuit composed of combinational logic without feedback will always show the same output for a given set of inputs. TRUE / FALSE Justification:
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3 f. For pipelined execution, if multiple exceptions happen in the same clock cycle for different instructions, the hardware should set the EPC to address of the earliest issued instruction. TRUE / FALSE Justification: g. To get good performance from future microprocessors in the next 5 to 10 years, SIMD via successors to SSE4 instructions could be as important to use as MIMD via more cores. TRUE / FALSE Justification: h. A particular memory access results in a page fault but not a protection error. Which of the following statements about this access is always true? Circle the answer. Always true / Not always true There was a TLB miss. Always true / Not always true The cache(s) will miss. Always true / Not always true
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cs61c_fa10_f - Fall 2010 CS61C Final Your Name: _ Your TA:...

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