Chapter3_3 - Chapter 3(Lect 3 Gate-Level Minimization NAND and NOR Implementation NAND Circuits NOR Circuits XOR and Parity Checking In most cases

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Chapter 3 (Lect 3) Gate-Level Minimization NAND and NOR Implementation NAND Circuits NOR Circuits XOR and Parity Checking
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
In most cases digital circuits are constructed using NAND and NOR gates rather than AND and OR gates NAND and NOR gates are simpler to manufacture lower cost take up less real estate Any of the three primitive logic operations, AND, OR, and NOT can be constructed using NAND or NOR gates We will develop a system to go from a AND, OR, NOT circuit representation to the NAND and NOR representations
Background image of page 2
NAND Representations F= F= F=
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
NOR Representations F= F= F=
Background image of page 4
NOT gates at inputs can be drawn as circles or simply NOT gate: Also notice: For Gates Then (A’B’) = (A’+B’) =
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Schematically going from AND-OR to NAND: 1. Express function in SOP or POS 2. Complement all OR gate inputs and the outputs of any gates, or literals connected to the OR inputs. 3. Replace AND-NOT gates with NANDs 4. Replace NOT-ORs with NANDs 5. Replace NOT-OR-NOT with NAND NAND-INVERTOR combinations A B' C D F E
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 12/15/2011 for the course E 202 taught by Professor Staff during the Fall '11 term at University of Alabama - Huntsville.

Page1 / 18

Chapter3_3 - Chapter 3(Lect 3 Gate-Level Minimization NAND and NOR Implementation NAND Circuits NOR Circuits XOR and Parity Checking In most cases

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online