Chapter4_4 - Chapter 4 (Lect 4) Encoders Multiplexers...

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Chapter 4 (Lect 4) Encoders Multiplexers Three-State Gates More Verilog
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Encoder: an encoder is the inverse of a decoder, it has 2 n or fewer input lines and n output lines Recall: 2 – 4 line decoder Inputs Outputs xy D 0 D 1 D 2 D 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 Inputs Outputs D 0 D 1 D 2 D 3 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 encoder:
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Encoder: Inputs Outputs D 0 D 1 D 2 D 3 xy 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 x = D 2 + D 3 y = D 1 + D 3 D0 D1 D2 D3 x y Issues: 1. Both outputs are 0, when D 0 is 1 or when all inputs are 0. 2. Only one input can be high at any given time or ambiguity occurs Solution: priority encoder and one additional output
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Priority Encoder: a priority encoder includes a priority function which acts to ensure if two or more inputs are high at the same time, the input with highest priority will take precedence Inputs Outputs D 0 D 1 D 2 D 3 xy 1000 0 0 0100 0 1 0010 1 0 0001 1 1 Inputs Outputs D 0 D 1 D 2 D 3 x y V 0 0 0 0 X X 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
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Inputs Outputs D 0 D 1 D 2 D 3 x y V 0 0 0 0 X X 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 D 0 D 1 D 2 D 3 00 01 11 10 00 01 10 D 0 D 1 D 2 D 3 00 01 10 00 01 10 x = y =
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Priority Encoder: x = D 2 + D 3 y = D 3 + D 1 D 2 V = D 0 + D 1 + D 2 + D 3 D0 D1 D2 D3 x y V Priority Event Alarm 1H e a v y Rain 00 2 Thunderstorm 01 3 Severe Thunderstorm 10 4 Tornado 11
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Multiplexers: multiplexers (aka MUX, data selector) are combinational circuits that select
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This note was uploaded on 12/15/2011 for the course E 202 taught by Professor Staff during the Fall '11 term at University of Alabama - Huntsville.

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Chapter4_4 - Chapter 4 (Lect 4) Encoders Multiplexers...

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