Chapter6_2 - Chapter 6 (Lect 2) •Ripple Counters...

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Unformatted text preview: Chapter 6 (Lect 2) •Ripple Counters •Binary counter •BCD counter •Synchronous Counters •Binary counter •up-down counter •Parallel Load counter Counter: Registers that go through a predefined set of states as a result of the application of input pulses Ripple counters: flip-flop output transitions serve as the clock inputs of other counters. Asynchronous! Trigger on Negative edge of clock pulse for up-count Trigger on Positive edge of clock pulse for down-count Synchronous counters: a common clock signal is received at the clock inputs of all flip-flops Can be Negative or Positive edge trigger, does not influence the direction of the count Binary Ripple Counter: n-bit binary counter requires n flip-flops, Note neg-edge triggers on CLK inputs, 1 to 0 transition acts to trigger, a positive clk edge trigger on a ripple counter causes a count down, recall T = 1 causes complement clock logic 1 A3 Clk Q R T Q A2 Clk Clk R T T R Clk reset R A1 T Q A0 Binary Ripple Counter: with D flip-flops clock reset A2 Clk Clk A3 R Q’ D Q D R Q’ Clk Clk R Q’ D Q R Q’ A1 D Q A0 BCD Ripple Counter: 0-9 aka decade counter J count J Clk K A1 0 Q(t) 0 1 0 reset 1 A0 0 0 1 set 1 J Clk K K 1 Q’(t) Count initial 1 2 J Clk K A2 3 4 5 J Clk K A3 6 7 8 9 logic 1 10 Q(t+1) no change Complement A3 A2 A1 A0 0 0 0 0 Cascading decade counters BCD counter A3 A2 A1 A0 BCD counter A3 A2 A1 A0 BCD counter A3 A2 A1 A0 count Synchronous Binary counter: Design 3-bit up-counter with jk’s, note synchronous counters can be positive or negative edge triggered, does not change the direction of count as it does for ripple counter State Diagram: count 0 - 7, return to 0 Synchronous Binary counter: Design 3-bit up-counter with jk’s, State Table Current state A A Q(t) Current state B C B C JA KA JB KB JC KC Q(t+1) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 Synchronous Binary counter: Design 3-bit up-counter with jk’s, Current state Current state A A B C B C JA KA 0 0 0 0 0 1 0 X 0 0 1 0 1 0 0 1 1 1 0 0 1 X 1 0 0 1 0 1 1 1 0 X 0 1 1 0 1 1 1 0 0 0 X 1 11 10 01 11 10 X 0 1 1 1 01 X 0 1 0 1 00 0 X 0 1 1 A 0 X 0 1 0 BC 0 1 JA = BC A 00 0 1 KA = Synchronous Binary counter: Design 3-bit up-counter with jk’s, Current state Current state A A B C B C JB KB 0 0 0 0 0 1 0 X 0 0 1 0 1 0 0 1 1 1 0 0 X 1 1 0 0 1 0 1 1 1 0 1 X 1 1 0 1 1 1 0 0 0 X 1 11 10 01 11 10 X 0 1 1 1 01 0 X 1 0 1 00 X 0 0 1 1 A 1 X 0 1 0 BC 0 1 JB = BC A 00 0 1 KB = Synchronous Binary counter: Design 3-bit up-counter with jk’s, Current state Current state A A B C B C JC KC 0 0 0 0 0 1 1 X 0 0 1 0 1 0 0 1 1 1 0 0 X 1 1 0 0 1 0 1 1 1 0 X 1 1 1 0 1 1 1 0 0 0 X 1 11 10 01 11 10 1 X 1 1 1 01 1 X 1 0 1 00 1 X 0 1 1 A X 1 0 1 0 BC 0 1 JC = BC A 00 0 1 KC = Synchronous Binary counter: Design 3-bit up-counter with jk’s, Circuit: Synchronous Binary counter: Design 3-bit down-counter with jk’s, State Diagram: count 7 - 0, return to 7 Synchronous Binary counter: Design 3-bit down-counter with jk’s, State Table Current state A A Q(t) Current state B C B C JA KA JB KB JC KC Q(t+1) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 Synchronous Binary counter: Design 3-bit down-counter with jk’s, Current state Current state A A B C B C JA KA 1 1 1 1 1 0 X 0 1 1 0 1 0 1 1 0 0 0 1 1 X 1 0 1 1 0 1 0 0 0 1 0 X 0 0 1 0 0 0 1 1 1 1 X 11 10 01 11 10 0 X 0 0 0 01 0 X 0 1 0 00 X 0 1 0 0 A X 0 1 0 1 BC 0 1 JA = BC A 00 0 1 KA = Synchronous Binary counter: Design 3-bit down-counter with jk’s, Current state Current state A A B C B C JB KB 1 1 1 1 1 0 X 0 1 1 0 1 0 1 1 0 0 0 1 1 1X 0 1 1 0 1 0 0 0 1 X 1 0 0 1 0 0 0 1 1 1 1 X 11 10 01 11 10 0 X 0 0 0 01 X 0 0 1 0 00 0 X 1 0 0 A X 1 1 0 1 BC 0 1 JB = BC A 00 0 1 KB = Synchronous Binary counter: Design 3-bit down-counter with jk’s, Current state Current state A A B C B C JC KC 1 1 1 1 1 0 X 1 1 1 0 1 0 1 1 0 0 0 1 1 1X 0 1 1 0 1 0 0 0 1 1X 0 0 1 0 0 0 1 1 1 1 X 11 10 01 11 10 X 1 0 0 0 01 X 1 0 1 0 00 X 1 1 0 0 A 1X 1 0 1 BC 0 1 JC = BC A 00 0 1 KC = Synchronous Binary counter: Design 3-bit down-counter with jk’s, Circuit: Synchronous Binary counter: Design 3-bit up-down-counter A B C J Clk K J Clk K J Clk K Single Circuit: clk logic 1 control Synchronous Parallel Load Counter: Can be used to generate any count sequence from 0 to 2n - 1. A3 A2 A1 A0 Clear Load Count Function 0 c_out CLK X X X Clear to 0 count load 4-bit counter 1 1 X Load inputs clear 1 0 1 Count 1 0 0 Hold CLK c_out is used to cascade counters, becomes 1 when all outputs are 1. data input A3 A2 A1 A0 What type of count? load count 4-bit counter clear CLK inputs = 0 What you should know 1. Be able explain the differences between Ripple and Synchronous counters 2. Understand the role of the clock signal in Ripple counters 3. Be able to design a up-down Synchronous counter using JK flip-flops ...
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