Chapter6_3andCh7 - Chapter 6 (Lect 3) Counters Continued...

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Chapter 6 (Lect 3) Counters Continued Unused States Ring counter Implementing with Registers Implementing with Counter and Decoder
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Sequential Logic and Unused States Not all states need to be used Can be used as don’t care conditions Risk Entering unused state accidently Never returning to a valid state Solution Assign unused states Use unused states as don’t cares--and test unused states of completed design--Validate as self-correcting Self-correcting Name given to a sequential circuit that returns to a valid state after entering an unused state Note returning to a valid state may require more than one clock cycle
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Unused States example: 000 100 001 010 110 101 Want State Table Current state A B C Current state B C J K A J B K B J C K C 0 0 00 0 10 X 0 X 1 X 0 0 1 X 1 X X1 0 1 01 0 X 0 X 1 0 0 1X 0 0 X 1 X 1 0 11 1 0X 0 1 X 1 1 0 1 X 1 0 X State Table and K-maps give J A = B K A = B J B = C K B = 1 J C = B’ K C = 1
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Equations and Circuit Check unused states Q( t ) Q (t+1) J K 0 00 X 0 11 X 1 0X 1 1 1X 0 J Clk K J Clk K J Clk K A B C clk logic 1 011 111
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Ring Counters constructed from shift-registers or the combination of counters and decoders counters in general are frequently used to generate timing signals Examples Update--track-- update time in software 10 ms clock signal 4-bit counter (edge trigger) return to zero count = 160 ms elapsed Determining lapsed time of event Detecting input signal
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Chapter6_3andCh7 - Chapter 6 (Lect 3) Counters Continued...

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