Test3_5200_sol - Name ELEC 5200/ELEC 6200 Computer...

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Name __________________________________________________________________ ELEC 5200/ELEC 6200 Computer Architecture and Design Class Test 3, December 3, 2004 Total 24 points Broun 306, 8:00-8:50AM Instructions: This test contains four pages. Please write your name on top of each page. Read all questions before writing your answers and attempt all four (4) questions. Answers should be written directly on the question sheets in the spaces provided. Be sure to revise your answers before turning them in. Turn in all sheets (even if portions are blank) and any extra pages you have used. Thank you. Problem 1: 6 points (a) What is the difference between a signal and a variable in VHDL? (2 points) Answer: A signal assignment takes place either after an amount of time or after a delta delay. A variable assignment has no delay, it happens immediately at the current simulation time. Also, variables can be declared and used only inside a process statement. (b) Define sensitivity list for a process. (2 points) Answer: A set of signals to which the process is sensitive is defined as the sensitivity list. In other
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