583L5 - EECS 583 Class 5 Hyperblocks, Control Height...

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EECS 583 – Class 5 Hyperblocks, Control Height Reduction University of Michigan September 21, 2011
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- 1 - Reading + Announcements Material Reminder – HW 1 due Friday at midnight » Submit uniquename_hw1.tgz file to andrew.eecs.umich.edu:/y/submit/ » Talk to Daya in office hours Thurs or Fri if having trouble My office hours today – cancelled due to industry visitors Today’s class » " Effective Compiler Support for Predicated Execution using the Hyperblock", S. Mahlke et al., MICRO-25, 1992. » "Control CPR: A Branch Height Reduction Optimization for EPIC Processors", M. Schlansker et al., PLDI-99, 1999. Material for next Monday » Compilers: Principles, Techniques, and Tools , A. Aho, R. Sethi, and J. Ullman, Addison-Wesley, 1988. (Sections: 10.5, 10.6, 10.9, 10.10)
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- 2 - Class Problem From Last Time - Answer if (a > 0) { r = t + s if (b > 0 || c > 0) u = v + 1 else if (d > 0) x = y + 1 else z = z + 1 } a. Draw the CFG b. Compute CD c. If-convert the code BB2 BB3 BB1 BB5 BB6 BB7 BB4 BB8 a <= 0 a > 0 b > 0 b <= 0 c <= 0 c > 0 d > 0 d <= 0 BB CD 1 - 2 1 3 -2 4 -3 5 2,3 6 -4 7 4 8 - p3 = 0 p1 = CMPP.UN (a > 0) if T r = t + s if p1 p2,p3 = CMPP.UC.ON (b > 0) if p1 p4,p3 = CMPP.UC.ON (c > 0) if p2 u = v + 1 if p3 p5,p6 = CMPP.UC.UN (d > 0) if p4 x = y + 1 if p6 z = z + 1 if p5
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- 3 - When to Apply If-conversion? Positives » Remove branch No disruption to sequential fetch No prediction or mispredict No use of branch resource » Increase potential for operation overlap » Enable more aggressive compiler xforms Software pipelining Height reduction Negatives » Max or Sum function applied when overlap Resource usage Dependence height Hazard presence » Executing useless operations BB2 BB4 BB6 BB5 BB1 BB3 80 20 10 90 10 90 10 80 20 10
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- 4 - Negative 1: Resource Usage BB2 BB4 BB1 BB3 60 40 100 60 40 Case 1: Each BB requires 3 resources Assume processor has 2 resources No IC: 1*3 + .6*3 + .4*3 + 1*3 = 9 9 / 2 = 4.5 = 5 cycles IC: 1(3 + 3 + 3+ 3) = 12 12 / 2 = 6 cycles 100 Resource usage is additive for all BBs that are if-converted Case 2: Each BB requires 3 resources Assume processor has 6 resources No IC: 1*3 + .6*3 + .4*3 + 1*3 = 9 9 / 6 = 1.5 = 2 cycles IC: 1(3+3+3+3) = 12 12 / 6 = 2 cycles BB1 BB2 if p1 BB3 if p2 BB4
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- 5 - Negative 2: Dependence Height BB2 BB4 BB1 BB3 60 40 100 60 40 Case 1: height(bb1) = 1, height(bb2) = 3 Height(bb3) = 9 , height(bb4) = 2 No IC: 1*1 + .6*3 + .4*9 + 1*2 = 8.4 IC: 1*1 + 1*MAX(3,9) + 1*3 = 13 100 Dependence height is max of for all BBs that are if-converted (dep height = schedule length with infinite resources) BB1 BB2 if p1 BB3 if p2 BB4 Case 2: height(bb1) = 1, height(bb2) = 3 Height(bb3) = 3 , height(bb4) = 2 No IC: 1*1 + .6*3 + .4*3 + 1*2 = 6 IC: 1*1 + 1*MAX(3,3) + 1*2 = 6
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- 6 - Negative 3: Hazard Presence BB2 BB4 BB1 BB3 60 40 100 60 40 Case 1: Hazard in BB3 No IC : SB out of BB1, 2, 4, operations In BB4 free to overlap with those in BB1 and BB2 IC: operations in BB4 cannot overlap
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This note was uploaded on 12/26/2011 for the course EECS 583 taught by Professor Flinn during the Fall '08 term at University of Michigan.

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583L5 - EECS 583 Class 5 Hyperblocks, Control Height...

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