583L14 - EECS 583 Class 14 Modulo Scheduling Reloaded...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
EECS 583 – Class 14 Modulo Scheduling Reloaded University of Michigan October 31, 2011
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
- 1 - Announcements + Reading Material Project proposal – Due Friday Nov 4 » 1 email from each group: names, paragraph summarizing what you plan to do Today’s class reading » "Code Generation Schema for Modulo Scheduled Loops", B. Rau, M. Schlansker, and P. Tirumalai, MICRO-25, Dec. 1992. Next reading – Last class before research stuff! » “Register Allocation and Spilling Via Graph Coloring,” G. Chaitin, Proc. 1982 SIGPLAN Symposium on Compiler Construction, 1982.
Background image of page 2
- 2 - A B A C B A D C B A D C B A D C B A D C B D C D Review: A Software Pipeline A B C D Loop body with 4 ops Prologue - fill the pipe Epilogue - drain the pipe Kernel – steady state time Steady state: 4 iterations executed simultaneously, 1 operation from each iteration. Every cycle, an iteration starts and finishes when the pipe is full .
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
- 3 - Loop Prolog and Epilog Prolog Epilog Kernel Only the kernel involves executing full width of operations Prolog and epilog execute a subset (ramp-up and ramp-down) II = 3
Background image of page 4
- 4 - A0 A1 B0 A2 B1 C0 A B C D Bn Cn-1 Dn-2 Cn Dn-1 Dn Separate Code for Prolog and Epilog A B C D Loop body with 4 ops Prolog - fill the pipe Kernel Epilog - drain the pipe Generate special code before the loop (preheader) to fill the pipe and special code after the loop to drain the pipe. Peel off II-1 iterations for the prolog. Complete II-1 iterations in epilog
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
- 5 - Removing Prolog/Epilog Prolog Epilog Kernel II = 3 Disable using predicated execution Execute loop kernel on every iteration, but for prolog and epilog selectively disable the appropriate operations to fill/drain the pipeline
Background image of page 6
- 6 - Kernel-only Code Using Rotating Predicates A0 A1 B0 A2 B1 C0 A B C D Bn Cn-1 Dn-2 Cn Dn-1 Dn P[0] P[1] P[2] P[3] 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 A if P[0] B if P[1] C if P[2] D if P[3] A - - - A B - - A B C - A B C D - B C D - - C D - - - D P referred to as the staging predicate
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
- 7 - Modulo Scheduling Architectural Support Loop requiring N iterations » Will take N + (S – 1) where S is the number of stages 2 special registers created » LC: loop counter (holds N) » ESC: epilog stage counter (holds S) Software pipeline branch operations » Initialize LC = N, ESC = S in loop preheader » All rotating predicates are cleared » BRF.B.B.F While LC > 0, decrement LC and RRB, P[0] = 1, branch to top of loop This occurs for prolog and kernel If LC = 0, then while ESC > 0, decrement RRB and write a 0 into P[0], and branch to the top of the loop This occurs for the epilog
Background image of page 8
Execution History With LC/ESC LC ESC P[0] P[1] P[2] P[3] 3 3 1 0 0 0 A 2 3 1 1 0 0 A B 1 3 1 1 1 0 A B C 0 3 1 1 1 1 A B C D 0 2 0 1 1 1 - B C D 0 1 0 0 1 1 - - C D 0 0 0 0 0 1 - - - D A if P[0]; B if P[1]; C if P[2]; D if P[3]; P[0] = BRF.B.B.F; LC = 3, ESC = 3 /* Remember 0 relative!! */ Clear all rotating predicates P[0] = 1 4 iterations, 4 stages, II = 1, Note 4 + 4 –1 iterations of kernel executed
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 35

583L14 - EECS 583 Class 14 Modulo Scheduling Reloaded...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online