lecture4

# lecture4 - ECE 4514 Digital Design II Spring 2007 Lecture 4...

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ECE 4514 Digital Design II Spring 2007 Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling Lecture 4: Gate Level Modeling Patrick Schaumont

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Gate-level Modeling b In this lecture we focus on modeling and simulation of gate networks b We will use structural modeling techniques b We will use delay modeling to estimate the delay of a circuit Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling b We will discuss several examples: s bit comparator s byte comparator s latch s master/slave flip-flop
Outline b Logic Primitive Gates b Instantiation, Fanout, Fanin, Arrays of gates b Truth Tables (X, Z) b Delay Models s Signal propagation in gates Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling s Delay modeling b Example Models: s Bit-comparator, Word-comparator s Latches and Flip-flops

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Primitive Gates b A primitive is a module which you do not have to describe as the simulator already knows it b There are 14 different primitive gates in Verilog s 8 of them are for logic functions (focus of this class) s 4 of them are for modeling tri-state signals s 2 of them are enance signal strength Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling b New primitive gates can be added s User Defined Primitives (Chapter 12 Palnitkar)
Standard Logic Functions and(out, in1, in2) nand(out, in1, in2) or(out, in1, in2) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling nor(out, in1, in2) xor(out, in1, in2) xnor(out, in1, in2) buf(out, in) not(out, in)

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More than two inputs, still a primitive and(out, in1, in2) nd(out, in1, in2, in3) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling and(out, in1, in2, in3) and(out, in1, in2, in3, in4, in5)
NAND Truth Table b Must deal with 'Z' and 'X' input (4-valued logic) b Z is undefined (floating), X is unknown in2 0 1 X Z 1 1 Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling in1 in2 out in1 0 1 X Z 1 0

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NAND Truth Table b Must deal with 'Z' and 'X' input (4-valued logic) b Z is undefined (floating), X is unknown in2 0 1 X Z 1 1 1 1 Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling in1 in2 out in1 0 1 X Z 1 0 1 1 With any input '0', ouput MUST be '1'.
NAND Truth Table b Must deal with 'Z' and 'X' input (4-valued logic) b Z is undefined (floating), X is unknown in2 0 1 X Z 1 1 1 1 Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling in1 in2 out in1 0 1 X Z 1 0 1 1 X X X X With an input '1', the ouput may be either '1' or '0', (we don't know unless we know the value of the other input)

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b Must deal with 'Z' and 'X' input (4-valued logic) b Z is undefined (floating), X is unknown in2 0 1 X Z 1 1 1 1 Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 4: Gate-level Modeling in1 in2 out in1 0 1 X Z 1 0 1 1 X X X X X
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lecture4 - ECE 4514 Digital Design II Spring 2007 Lecture 4...

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