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lecture5 - ECE 4514 Digital Design II Spring 2008 Lecture 5...

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ECE 4514 Digital Design II Spring 2008 Lecture 5: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works How HDL simulation works A tool & methodology Lecture Patrick Schaumont
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Today's topic boxshadowdwn We look at the simulation mechanism of Verilog Verilog Model of a hardware circuit (many gates) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works Modelsim Verilog Simulator Sequential Machine Simulator creates the illusion of parallel activites in model Simulator is a software program running on a PC
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HDL simulation is different from C execution boxshadowdwn Need to express concurrency (things happening simultaneously) boxshadowdwn Need to model time boxshadowdwn Need to model non-standard wordlengths Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works boxshadowdwn Need to model non-standard values (X,Z) boxshadowdwn Need organization in modules rather than functions
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HDL simulation is different from C execution boxshadowdwn Need to express concurrency (things happening simultaneously) boxshadowdwn Need to model time boxshadowdwn Need to model non-standard wordlengths Simulation Time + Concurrency Model (events, cycles, ..) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works boxshadowdwn Need to model non-standard values (X,Z) boxshadowdwn Need organization in modules rather than functions New data types, custom syntax
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Focus of this lecture boxshadowdwn Need to express concurrency (things happening simultaneously) boxshadowdwn Need to model time Simulation Time + Concurrency Model (events, cycles, ..) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works Understand the concept of event driven simulation Understand how gate-level models are simulated Understand how behavioral models are simulated Objectives:
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The need for concurrent hardware models a b Let's write a simulation for this circuit in C clk Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works int a, b; void clock_cycle() { a = b; b = a; } We create a function clock_tick which will be called for each clock cycle. Is the following a correct implementation of this function?
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The need for concurrent hardware models a b Let's write a simulation for this circuit in C clk Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 5: How HDL Simulation Works int a, b; void clock_cycle() { a = b; b = a; } No! a and b will have the same value after one call We create a function clock_tick which will be called for each clock cycle. Is the following a correct implementation of this function?
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A better solution a b Let's write a simulation for this circuit in C clk Is this better?
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