lecture8 - ECE 4514 Digital Design II Spring 2008 Lecture...

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ECE 4514 Digital Design II Spring 2008 ecture 8: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths Lecture 8: Multiplexed Datapaths A Methods Lecture Patrick Schaumont
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Today's topic b An design method that uses dataflow modeling b A Design Method s A canned sequence of steps, commands s Is easy to learn, easy to remember, easy to apply s Allows a designer to concentrate on design rather than on tools Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths b The method we will discuss is called Multiplexed Datapaths
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Multiplexed Datapaths - Disclaimer b We will cover very specific Verilog modeling guidelines to build hardware modules called 'multiplexed datapaths' b Not the only way to build hardware in Verilog s We will see other 'design methods' later b But, if you use the 'multiplexed datapath' method, you Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths MUST stick to the following guidelines
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What is a multiplexed datapath ? b A module with a single clk and rst input b Zero or more inputs, one or more outputs b Edge-triggered flip-flops b Outputs depend only on registers put put put Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths clk input input input output output combinational logic + edge-triggered flipflops rst
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Why single-clock ? b A module with a single clk and rst input b Zero or more inputs, one or more outputs b Edge-triggered flip-flops b Outputs depend only on registers Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths Simplifies generation and distribution of clock signal in the implementation
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Why edge-triggered flip-flops ? b A module with a single clk and rst input b Zero or more inputs, one or more outputs b Edge-triggered flip-flops b Outputs depend only on registers Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths A single type of storage module simplifies test A single type of reset signal simplifies initialization
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Why outputs depend only on registers ? b A module with a single clk and rst input b Zero or more inputs, one or more outputs b Edge-triggered flip-flops b Outputs depend only on registers ake sure that system vel delay, i.e. critical path, Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths Make sure that system-level delay, i.e. critical path, is just max(module-level delay), not sum(module-level delay) module 1 module 2 module 3 delay 1 ~ logic1 delay delay 2 ~logic2 delay delay 3 ~logic3 delay logic 1 logic 2 logic 3 System Delay = max(delay1, delay2, delay3) + routing_delay
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Template for a Multiplexed Datapath Datapath State Dataflow Expressions Inputs Next State Dataflow Expressions Outputs Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 8: Multiplexed Datapaths Previous State
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How to model an edge-triggered register module a_module(q, rst, clk, d);
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lecture8 - ECE 4514 Digital Design II Spring 2008 Lecture...

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