lecture9 - ECE 4514 Digital Design II Spring 2008 Lecture 9...

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ECE 4514 Digital Design II Spring 2008 Lecture 9: Review of Key Ideas, System Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 9: System Commands and Testbenches Commands and Testbenches A Language Lecture Patrick Schaumont
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Iterating the Key Ideas boxshadowdwn Verilog is a modeling language. It cannot express hardware directly. It describes the activities of a hardware implementation. module a_module(q, rst, clk, d); output q; input rst; input clk; input d; This fragment describes the behavior of a flip-flop but does not describe the flip-flop itself! Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 9: System Commands and Testbenches wire next_r1; reg r1; always @( posedge clk or negedge rst) if (rst) r1 = next_r1; else r1 = 0; assign next_r1 = d; assign q = r1; endmodule It describes the flip-flop using variables (reg), nets (wire), and processes (always, assign). VERILOG = 'VERIfy LOGic'
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Verilog Simulation Cycle Nets Variables are in the sensitivity list of Gates execute and make changes to Processes Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 9: System Commands and Testbenches Behavioral code
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Iterating the Key Ideas Simulation Time and Variables/Nets in Verilog variable (reg) once assigned, will remember what is stored into it startup value = X value at time T defined by the previous assignment on the variable Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 9: System Commands and Testbenches wire (net) can hold a value only at the current time (time = T) startup value = X value at time T defined by the variable that drives the wire
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Always and Assign always blocks - within block statement (begin .. end), executes sequentially - will only stop when waiting for an event (wait, @, #) - assignment (=) only on variables (reg) ( 'procedural assignment ') Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 9: System Commands and Testbenches - intra-assignment delay possible assign statement - assignment (=) only on nets (wire) ( 'continuous assignment' ) - no intra-assignment delay possible
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Modeling Styles gate-level - model hardware with structure, by interconnecting primitives multiplexed data-path Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 9: System Commands and Testbenches - model combinational logic with assign expressions, and flip-flops with wire/reg combination.
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