lecture12 - ECE 4514 Digital Design II Spring 2008...

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ECE 4514 Digital Design II Spring 2008 Behavioral Modeling II: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops Conditionals and Loops A Language Lecture Patrick Schaumont
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Behavioral Modeling so far b Procedural statements (lecture 2 and on) s Always and Initial constructs s Sequential block statements b Procedural Assignments s Blocking assignments (lecture 2 and on) s Non-blocking assignments (lecture 10) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops b Event control statements (lecture 5) s @ s wait s # NNN
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Today b Conditional statements s if-then-else s case b Loop statement b Parallel block statements, named block statements Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops b Plus a few useful structural techniques s Generate construct b Palnitkar: 7.4 - 7.10 b IEEE 1364: 9.4 - 9.8, 12.4
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Today b Conditional statements s if-then-else s case b Loop statement b Parallel block statements, named block statements Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops b Plus a few useful structural techniques s Generate construct b Palnitkar: 7.4 - 7.10 b IEEE 1364: 9.4 - 9.8, 12.4
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Conditional statement reg [7:0] a, b, max; always @( posedge clk) begin max = b; if (a > b) max = a; end True if non-zero False if zero, X or Z Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops always @(posedge clk) begin if (a > b) max = a; else max = b; end
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Conditional statement reg [7:0] a, b, max; always @( posedge clk) begin if (a > b) begin max = a; ... other statement . . end nd Use begin . . end to include multiple statements Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops end
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Nested if-then-else b Else associates with the innermost if reg [7:0] a, b, c, max; always @( posedge clk) begin if (b > a) if (b > c) max = b; Note that indentation does not imply association. erilog is context ee. Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops else max = c; else max = a; end How to change this association ? Verilog is context-free.
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Nested if-then-else b Use begin--end to change association reg [7:0] a, b, c, max; always @( posedge clk) begin if (b > a) begin if (b > c) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops max = b; end else max = a; end
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b Frequently used as a case-decoding statement reg [7:0] a, b, c, max; always @( posedge clk) begin if (a < 10) begin // . .. when a < 10 end Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 12: Behavioral Modeling: Conditionals and Loops else if (a < 20) begin // . .. when a >= 10 and a < 20
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This note was uploaded on 12/24/2011 for the course ECE 4514 taught by Professor Staff during the Fall '08 term at Virginia Tech.

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lecture12 - ECE 4514 Digital Design II Spring 2008...

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