lecture15 - ECE 4514 Digital Design II Spring 2008 ecture...

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Unformatted text preview: ECE 4514 Digital Design II Spring 2008 ecture 15: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control Lecture 15: FSM-based Control A Design Lecture Patrick Schaumont Overview b Finite State Machines s Verilog Mapping: one, two, three always blocks b State Encoding s User-defined or tool-defined s State encoding techniques: one-hot, user-defined, gray ynthesis Issues Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control b Synthesis Issues s Default state assignment s Safe Implementations s Next-state logic: RAM or LUT b FSM-based control of Datapath (gcd) Finite State Machine Template b Sequential Machine defined by s Set of Inputs and Outputs s Set of States s Initial State (reset function) s State Transitions Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control inputs outputs next-state function state register output function ( in case of Mealy Machine) Design Process Designer Creates State Transition Graph Extract State Transition Table Choose State Encoding Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control Create Next State Logic Design Process Designer Creates State Transition Graph Extract State Transition Table Choose State Encoding Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control Create Next State Logic full-structural Verilog Model (design all gates) Design Process Designer Creates State Transition Graph Extract State Transition Table Choose State Encoding Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control Create Next State Logic Structural Verilog Model Behavioral Verilog Model (with explicit state encoding) Design Process Designer Creates State Transition Graph Extract State Transition Table Choose State Encoding We will focus on and Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control Create Next State Logic Structural Verilog Model Behavioral Verilog Model (with explicit state encoding) Behavioral Verilog Model (with automatic state assignment) Example FSM Design b Create an FSM that turns the first '1' of a string of consecutive '1' into a '0'. 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 Input Each clock cycle, a new input is provided Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 Output Example FSM Design b How many states? 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 Input Output Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control Example FSM Design b How many states? current state 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 Input Output Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 15: FSM-based Control 3 states x ( = I have not seen a '1') 1 ( = I have seen a single '1') 1 ( = I have seen more then a single '1') Example FSM Design...
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lecture15 - ECE 4514 Digital Design II Spring 2008 ecture...

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