lecture18 - ECE 4514 Digital Design II Spring 2008 Lecture...

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Unformatted text preview: ECE 4514 Digital Design II Spring 2008 Lecture 18: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Optimizing Area A Tools/Methods Lecture Patrick Schaumont Optimization and Backend Verification b Previous 4 lectures (Lecture 13-16): s How to get Verilog mapped into hardware b Next 2 lectures: s How to optimize Verilog for hardware implementation s Today (Lecture 17): Optimize for (smaller) area s Thursday (Lecture 18): Optimize for (higher) performance Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Why do we need optimization? b A given algorithm can be implemented in many different ways in digital hardware b Each implementation is characterized by s A certain area (In FPGA: Slices) s A certain cycle budget (the amount of cycles needed to complete one iteration through the algorithm) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area b The application domain and other external requirements provide constraints for the area or the performance (=cycle_budget-1 ) s 'Create a circuit not larger than can fit in a Spartan3S100 FPGA ...' (area) s 'Create an implementation that can complete at least 500 million additions per second ..' (performance) Area-Delay Product: Generic Optimality Criterion b Area-Delay Product = Area of a circuit times the cycle budget for that circuit Design XYZ in out Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area 400 Slices 20 cycles Area-Delay = 8000 Slices.cycles A lower Area-Delay product is better Area-Delay Product Area (eg. Slices) Assume that a given design can be implemented in 5 different ways, and that all of them have the same Area-Delay product. All these points lie on a hyperbole, since Area x Delay = Constant ow do you select which specific Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Delay = Performance-1 (e.g. cycles) How do you select which specific implementation to use? By introducing CONSTRAINTS Area-Delay Product b An Area constraint Area (eg. Slices) Area Constraint Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Delay = Performance-1 (e.g. cycles) 'Smaller then ...' Area-Delay Product b An Area constraint Area (eg. Slices) Most optimal point (smallest delay) for given area constraint Area Constraint Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Delay = Performance-1 (e.g. cycles) 'Smaller then ...' Area-Delay Product b A Performance Constraint Area (eg. Slices) Performance Constraint Faster then ...' Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Delay = Performance-1 (e.g. cycles) Area-Delay Product b A Performance Constraint Area (eg. Slices) Performance Constraint Faster then ...' Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 18: Optimizing Area Delay = Performance-1 (e.g. cycles) Most optimal point (smallest area) for given performance constraint Area-Delay Product...
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lecture18 - ECE 4514 Digital Design II Spring 2008 Lecture...

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