lecture19 - ECE 4514 Digital Design II Spring 2008 Lecture...

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Unformatted text preview: ECE 4514 Digital Design II Spring 2008 Lecture 19: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Optimizing Performance A Tools/Methods Lecture Patrick Schaumont Area-Delay Product Area (eg. Slices) Suboptimal Points Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Delay = Performance-1 (e.g. cycles) Optimal Points Area-Delay Product Area (eg. Slices) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Delay = Performance-1 (e.g. cycles) Area Constraint Best Choice Area-Delay Product Area (eg. Slices) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Delay = Performance-1 (e.g. cycles) Delay Constraint Best Choice Optimizing Performance - Overview b Performance factors of a digital design s Latency and Throughput s Delay = Clock Period * Cycle Count b What determines the minimum clock period? b Performance Optimizations you can do in Verilog arallel Computations Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance s Parallel Computations s Pipelining s Retiming b Summary Optimizing Area & Performance Performance (Delay) of a design b Two common definitions for the performance of a design s The time it takes to compute an output starting from a given input: Latency s The rate at which new outputs are produced (or the rate at which new inputs are consumed): Throughput s Depending on the application, you will need to optimize one r the other Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance or the other b The unit of Throughput and Latency is time (seconds). s If you find a number in cycles , you have to find the clock period T before you know the throughput or latency. b Performance = 1 / Throughput or 1 / Latency s We will use the generic term Delay s Delay = 1 / Performance Delay of a design b Latency = (cycles from I to O) * (clock period) s Example: System clock frequency = 20MHz ( = 50 ns period) Each output is available 10 clock cycles after a new input is provided s Latency = 10 * 50 ns = 500 ns Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Digital Synchronous Design f CLK Input Output 10 cycles Delay of a design b Throughput = (cycles between I) * (clock period) s Example: System clock frequency = 20MHz Each 5 clock cycles a new input is accepted s Throughput = 5 * 50 ns = 250 ns Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Digital Synchronous Design f CLK Input Output 5 cycles Delay = Cycle Count * Clock Period b Delay (either latency or throughput) has two components s Cycle Count. This quantity is controlled by the kind of Verilog that the designer writes s Clock Period. This quantity is determined by the synthesis tools that map the Verilog into an implementation Patrick Schaumont Spring 2008...
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This note was uploaded on 12/24/2011 for the course ECE 4514 taught by Professor Staff during the Fall '08 term at Virginia Tech.

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lecture19 - ECE 4514 Digital Design II Spring 2008 Lecture...

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