lecture19 - ECE 4514 Digital Design II Spring 2008 Lecture...

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ECE 4514 Digital Design II Spring 2008 Lecture 19: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Optimizing Performance A Tools/Methods Lecture Patrick Schaumont
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Area-Delay Product Area (eg. Slices) Suboptimal Points Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Delay = Performance -1 (e.g. cycles) Optimal Points
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Area-Delay Product Area (eg. Slices) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Delay = Performance -1 (e.g. cycles) Area Constraint Best Choice
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Area-Delay Product Area (eg. Slices) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Delay = Performance -1 (e.g. cycles) Delay Constraint Best Choice
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Optimizing Performance - Overview boxshadowdwn Performance factors of a digital design square4 Latency and Throughput square4 Delay = Clock Period * Cycle Count boxshadowdwn What determines the minimum clock period? boxshadowdwn Performance Optimizations you can do in Verilog square4 Parallel Computations Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance square4 Pipelining square4 Retiming boxshadowdwn Summary Optimizing Area & Performance
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Performance (Delay) of a design boxshadowdwn Two common definitions for the performance of a design square4 The time it takes to compute an output starting from a given input: Latency square4 The rate at which new outputs are produced (or the rate at which new inputs are consumed): Throughput square4 Depending on the application, you will need to optimize one or the other Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance boxshadowdwn The unit of Throughput and Latency is time (seconds). square4 If you find a number in cycles , you have to find the clock period T before you know the throughput or latency. boxshadowdwn Performance = 1 / Throughput or 1 / Latency square4 We will use the generic term Delay square4 Delay = 1 / Performance
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Delay of a design boxshadowdwn Latency = (cycles from I to O) * (clock period) square4 Example: System clock frequency = 20MHz ( = 50 ns period) Each output is available 10 clock cycles after a new input is provided square4 Latency = 10 * 50 ns = 500 ns Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Digital Synchronous Design f CLK Input Output 10 cycles
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Delay of a design boxshadowdwn Throughput = (cycles between I) * (clock period) square4 Example: System clock frequency = 20MHz Each 5 clock cycles a new input is accepted square4 Throughput = 5 * 50 ns = 250 ns Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 19: Optimizing Performance Digital Synchronous Design f CLK Input Output 5 cycles
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Delay = Cycle Count * Clock Period boxshadowdwn Delay (either latency or throughput) has two components square4 Cycle Count. This quantity is controlled by the kind of Verilog that the designer writes square4 Clock Period. This quantity is determined by the synthesis tools that map the Verilog into an implementation Cycle Count is fixed
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