lecture20 - ECE 4514 Digital Design II Spring 2008 Lecture...

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ECE 4514 Digital Design II Spring 2008 Lecture 20: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis Timing Analysis and Timed Simulation A Tools/Methods Lecture Patrick Schaumont
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Topics b Static and Dynamic Timing Analysis b Static Timing Analysis s Delay Model s Path Delay s False Paths s Timing Constraints Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis s b Dynamic Timing Analysis s s Delay back-annotation with SDF files s Demonstration
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Static and Dynamic Timing Analysis Digital Synchronous Design f CLK Input Output Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis b Suppose that we want to automatically find the maximum clock frequency of a given design s written in Verilog s and synthesized to a given technology b Approach 1: Static Timing Analysis = use analysis techniques on the netlist to define f clk,max b Approach 2: Dynamic Timing Analysis = use simulation and selected input stimuli to measure the slowest path
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Static and Dynamic Timing Analysis b Static Timing Analysis seems ideal, since it is done by a design tool that starts from the netlist and runs automatically b However, Static Timing Analysis may report pessimistic results and report delays that will never occur during operation b Dynamic Timing Analysis is nice, because we can combine it with the simulations which we do for functional verification Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis b However, Dynamic Timing Analysis may be too optimistic , in particular if we do not simulate the worst possible case (which may be hard to predict in a complex netlist) b In this lecture, we put the two techniques side-to-side
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Static Timing Analysis b STA looks for the worst of the following delays in a chip Delay from input to register Delay from register to register Delay from register to output Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis Combinational Logic Combinational Logic Combinational Logic IN OUT
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Static Timing Analysis b STA relies on a similar model as we discussed before Combinational Logic Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis T clk,min = T clk->Q + T Logic + T Routing + T Setup CLK Property of the component (flipflop) Property of the netlist Property of the component (flipflop)
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Static Timing Analysis b STA also takes delay on the clock connection into account. This is called clock skew. b The effect of clock skew is highly dependent on circuit topology Combinational Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 20: Timing Analysis Logic T clk,min = T clk->Q + T Logic + T Routing + T Setup - T Skew CLK T skew Here, skew works 'in favor' of us.
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Static Timing Analysis b STA also takes delay on the clock connection into account. This is called clock skew. b
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lecture20 - ECE 4514 Digital Design II Spring 2008 Lecture...

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