lecture22 - ECE 4514 Digital Design II Spring 2008 Lecture...

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ECE 4514 Digital Design II Spring 2008 Lecture 22: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics Design Economics: FPGAs, ASICs, Full Custom A Tools/Methods Lecture Patrick Schaumont
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Overview b Wows and Woes of scaling s The case of the Microprocessor s How efficiently does a microprocessor use transistors ? b Alternative Technologies: FPGA, ASIC, Full Custom s Energy Efficiency and Design Cost SIC Standard Cell Design Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics b ASIC Standard Cell Design b Full Custom Design b Future Challenges in Digital Design
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The Wows of scaling b Everybody is using Microprocessors because s PC's are everywhere s C compilers are everywhere s They get faster all the time s They get cheaper all the time Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics b All this is thanks to technology scaling
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Scaling enabled performance improvements Feature Size = Channel length L of a transistor Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Transistor Count Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Clock Frequency [Sima] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Integer Performance specint 92 [Sima] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Architecture Efficiency [Sima] Breakpoint Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Architecture Efficiency [Sima] Breakpoint Beyond this point, improvements have been obtained through faster clock frequency Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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The Woes of scaling b Scaling provides more transistors that operate faster s Can do more operations per second b However s More transistors working faster will consume more power (even when they're smaller) s Low-level electrical effects become dominant Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics s Wires do not improve with scaling
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Processor Power Consumption P dyn = a. C . V 2 . f clk Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Low level electrical effects become dominant dynamic power Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics static power
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Wires do not improve with scaling Chip Area reachable in a single clock cycle in technology N Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics Area reachable in a single clock cycle in technology N+1 Caused by scaled wire geometry (R increases)
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[SIA97] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics medium-long wire . . (43u @ 90nm =
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lecture22 - ECE 4514 Digital Design II Spring 2008 Lecture...

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