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lecture22 - ECE 4514 Digital Design II Spring 2008 Lecture...

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ECE 4514 Digital Design II Spring 2008 Lecture 22: Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics Design Economics: FPGAs, ASICs, Full Custom A Tools/Methods Lecture Patrick Schaumont
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Overview boxshadowdwn Wows and Woes of scaling square4 The case of the Microprocessor square4 How efficiently does a microprocessor use transistors ? boxshadowdwn Alternative Technologies: FPGA, ASIC, Full Custom square4 Energy Efficiency and Design Cost boxshadowdwn ASIC Standard Cell Design Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics boxshadowdwn Full Custom Design boxshadowdwn Future Challenges in Digital Design
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The Wows of scaling boxshadowdwn Everybody is using Microprocessors because square4 PC's are everywhere square4 C compilers are everywhere square4 They get faster all the time square4 They get cheaper all the time Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics boxshadowdwn All this is thanks to technology scaling
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Scaling enabled performance improvements [Weste & Harris] Feature Size = Channel length L of a transistor Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Transistor Count [Weste & Harris] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Clock Frequency [Sima] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Integer Performance specint 92 [Sima] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Architecture Efficiency [Sima] Breakpoint Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Microprocessor Architecture Efficiency [Sima] Breakpoint Beyond this point, improvements have been obtained through faster clock frequency Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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The Woes of scaling boxshadowdwn Scaling provides more transistors that operate faster square4 Can do more operations per second boxshadowdwn However square4 More transistors working faster will consume more power (even when they're smaller) square4 Low-level electrical effects become dominant square4 Wires do not improve with scaling Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Processor Power Consumption [Weste & Harris] P dyn = a. C . V 2 . f clk Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics
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Low level electrical effects become dominant dynamic power [Weste & Harris] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics static power
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Wires do not improve with scaling Chip Area reachable in a single clock cycle in technology N Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics Area reachable in a single clock cycle in technology N+1 Caused by scaled wire geometry (R increases)
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Wires even become slower than gates [SIA97] Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 22: Design Economics medium-long wire ..
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