lecture3 - ECE 4514 Digital Design II Spring 2007 Patrick...

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Unformatted text preview: ECE 4514 Digital Design II Spring 2007 Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter Lecture 3: Verilog Bread and Butter Patrick Schaumont Verilog b Difference between synthesis and simulation b Modules, module declarations and instantiation b Constants s Numbers b Data types Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter s Value Levels s Regs s Vectors s Arrays Synthesis and Simulation b To simulate a 4-bit counter module we used a testbench. ripple_carry_counter clk clk Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter some behavioral code reset q[0:3] q[0:3] reset This is Verilog This is Verilog This module is only needed for Simulation This module can be Simulated and Synthesized Synthesis and Simulation All possible Verilog Programs which are syntactically correct All possible Verilog Programs suitable for hardware simulation (i.e. deterministic behavior) Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter All possible Verilog Programs suitable for hardware synthesis (i.e. maps into gates) Synthesis and Simulation module syntst; reg b; initial begin b = 0; end Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter initial begin b = 1; end endmodule; This will simulate, but it's non-deterministic. meaning: if you use this code on a different Verilog simulator, the simulation may be different Synthesis and Simulation module syntst(clk); init clk; reg b; initial begin b = 0; #10 b = 1; nd This will simulate, but it's not synthesizable. Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter end endmodule; Analyzing top module <syntst>. WARNING:Xst:916 - "syntst.v" line 12: Delay is ignored for synthesis. Module <syntst> is correct for synthesis. Synthesizing Unit <syntst>. Related source file is "syntst.v". WARNING:Xst:647 - Input <clk> is never used. WARNING:Xst:653 - Signal <b> is used but never assigned. Tied to value 1. Unit <syntst> synthesized. Synthesis and Simulation module syntst(clk, q); input clk; output q; reg b; always @(posedge clk) egin This will synthesize Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter begin b = ~b; end assign q = b; endmodule Synthesis and Simulation b For now, we are focusing on simulation and writing correct Verilog code b Keep in mind: A correct simulation does not mean a correct implementation ... Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter Modules module name(portlist); port declarations; parameter declarations; wire declarations; reg declarations; variable declarations; Patrick Schaumont Spring 2008 ECE 4514 Digital Design II Lecture 3: Verilog Bread and Butter module instantations; dataflow statements; always blocks; initial blocks; tasks and functions; endmodule Modules...
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lecture3 - ECE 4514 Digital Design II Spring 2007 Patrick...

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