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# lecture14 - Lecture 15: Processor Design Why Everything...

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Unformatted text preview: Lecture 15: Processor Design Why Everything You’ve learned Matters Next Week •  Tue: 11:59pm Lab3 due •  Tue: No class, work on Lab3 •  Thur: Yes, we have lectures. Review of Last Lecture •  CombinaHonal vs. SequenHal Logic •  What are these logic units? –  Adder –  Traﬃc light controller –  Memory Building Memory and Registers •  Latches & Flip ﬂops •  What is the key diﬀerence between them? Clocked D Latches Truth table D CK Q 0 1 0 1 1 1 X 0 Q0 D ﬂip ﬂop Truth table D Q 0 ↑ 0 1 ↑ 1 X CS 30 CK 0,1 Q0 D ­Flip Flop vs. D ­Latch Truth table D CK Q 0 ↑ 0 1 ↑ 1 X 0,1 Q0 Truth table D CK Q 0 1 0 1 1 1 X 0 Q0 Latches & Flip ­Flops •  Latches are level sensiHve –  when the clock signal is high, and as long as the clock is high, the output can change if the input also changes •  FF are edge sensiHve. –  The output will only change according to he input when there is a rising/falling edge of the clock; note that for rising edge FF, changes happen during rising edge, and for falling edge FF, changes happen during falling edge, but not both. Another Group Exercise Pushing the Bubbles •  When a logic unit has just NAND/AND gates, you can convert it into using just NOR/OR/ NOT gate by bubble ­pushing –  Using DeMorgan’s Law •  The same applies to NOR/OR gates ...
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## This note was uploaded on 12/27/2011 for the course CMPSC 64 taught by Professor Zheng during the Fall '09 term at UCSB.

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