power4-overview

power4-overview - TACC/NPACI IBM Regatta-HPC (Power4)...

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The University of Texas at Texas Advanced Computing Center TACC/NPACI IBM Regatta-HPC (Power4) Overview Chona Guiang, Kent Milfeld, Avi Purkayastha and Jay Boisseau August 21, 2002
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 2 Background: TACC As An NPACI Resource Partner The Texas Advanced Computing Center (TACC) has provided HPC resources and services for 16 years to UT-Austin TACC has been a leading NPACI resource partner since Oct97 and has provided Cray T3E, Cray SV1, IBM SP2, and now IBM Regatta cycles to NPACI users TACC resource are available via the usual NPACI Allocations procedures TACC will teach HPC (and SciViz and Grid) training this Fall in Austin (the Live Music Capital of the World)
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 3 Outline Architecture and System Configuration Regatta Programming Environment Power4 Code Optimization
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 4 Architecture and System Configuration
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 5 Architecture & System Configuration Outline Processor Features (chip, core, cache/memory) Node Design (Multi-Chip Modules, MCM) MCM Memory Access (remote/local)
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 6 IBM Microprocessor Family Power 32-bit PowerPC 64-bit PowerPC 32-bit Chip series Power3 64-bit Power4 SOI Copper 1+ GHz 64-bit
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 7 Power4 Processor Features 64-bit Architecture Super Scalar, Dynamic Scheduling Speculative Superscalar Out-of-Order execution, In-Order completion “8 Instruction Fetch” but instructions are grouped for execution sustains five-issues per clock and 1 branch, up to 215 in flight. 2 LSU, 2 FXU, 2 FPU, 1 BXU, 1CRLXU 8 Prefetching Streams
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 8 Processor Features (cont.) 80 General Purpose Registers, 72 Float Registers Rename registers for pipelining Aggressive Branch Prediction 4KB or 16MB Page Sizes 3-Level Cache 1024 TLB entry Hardware Performance Counters
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 9 Processor Features: FPU 2 Floating Point Multiply/Add (FMA) Units 4 Flops/CP 6 CP FMA Pipeline 128-bit Intermediate Results (no rounding, default) IEEE Arithmetic 32 Floating Point Registers + 40 rename regs Hardware Square Root 38 CPs, Divide 32 CPs
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 10 Processor Features: Power4 Core I-cache BR CR FX1 LD1 LD2 FX2 FP1 FP2 BR/CR Issue Q FX/LD 1 Issue Q FX/LD2 Issue Q FP Issue Q Decode, Crack & Group Formation GCT BR Predict BR Scan I-cache IFAR St Q D-Cache Instr. Q
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 11 Processor Features: Instruction Execution Pipeline IF BP IC GD D0 D3 xfer D2 D1 MP MP MP MP F6 Xfer CP RF ISS EX WB Xfer RF ISS EA DC FMT WB Xfer RF ISS EX WB Xfer RF ISS WB BR LD/ST FX FP Instruction Crack & Group Formation Instruction Fetch Out-of-order Processing Interrupts & Flushes Branch Redirects
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TACC/NPACI IBM Regatta-HPC (Power4) Overview 12 Power4 Packaging: 2 Cores/Chip
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This note was uploaded on 12/27/2011 for the course CMPSC 140 taught by Professor Gilbert during the Fall '11 term at UCSB.

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power4-overview - TACC/NPACI IBM Regatta-HPC (Power4)...

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