Exam2-S06

Exam2-S06 - CPE 315 Spring 2006 Midterm 2 Single-Cycle...

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CPE 315 Spring 2006 Midterm 2 Single-Cycle Implementation ______/25 Pipelining ______/25 Dependencies ______/25 Performance ______/25 ______/100
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1. Single Cycle Implementation (25 pts) ___15 (a) Indicate clearly the datapaths (which includes the update to the pc) used for the jal instruction. In addition, add any wires, muxes, etc., that you needed to add to your lab to complete the implementation. Make sure you use the MIPS processor from class. op rs rt rd Meaning jr $s0 $s0 0 0 PC = $s0 ___10(b) We want to add the following instruction to our single-cycle implementation machine. op rs rt rd Meaning lwa $1, $2, $3 1 2 3 $3 = M[$1] + $2 Draw the data paths (including updating the PC) for this instruction. Add any wires, hard-coded values, components and/or muxes that would be necessary to implement this instruction. Also show any control that you need to add. Make sure you use the MIPS processor from class.
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2. Pipelining (25 pts) Assume the following latencies for the pipeline in the book: Fetch Decode1 Decode2 Execute1 Execute2 Memory WriteBack 4.1ns 2ns 2ns 3ns 3.5ns 4.2ns 2ns Pipeline register delay: .1 ns Assume regs are read in D1, and branches are decided in D2
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This note was uploaded on 12/27/2011 for the course CMPSC 154 taught by Professor Franklin during the Fall '09 term at UCSB.

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Exam2-S06 - CPE 315 Spring 2006 Midterm 2 Single-Cycle...

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