Lec1BFabNotes

Lec1BFabNotes - Fabrication Chapter 1, 2.19 Outline...

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Fabrication Chapter 1, 2.19
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Outline Fabrication Being practical ISA Types How the architecture affects the code
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Growing Silicon Silicon is a crystal grown in a vat It comes out the shape of a cylinder This is called an ingot
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Creating Chips Sliced into thin discs called wafers Etch grooves and pour metal, etc Cut the wafer into dies or chips A flaw is called a defect The percentage of good ones is yield wafer chip or die defect Yield: 8/10 = 80%
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Price vs Cost Price Selling price Little correlation to fabrication cost Cost Fabrication cost Design cost
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Cost Cost per die (CostPerWafer) / ((DiesPerWafer)*Yield) Dies per wafer (Wafer area / Die area) – wasted edge space Yield 1 / (1 + (DefectPerArea * DieArea/2)) 2 Cheapest when Yield is ( high ) and Dies per wafer are ( high )
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Current chip trends Shrinking Technology Reported in microns (width of wire) Each generation allows more to fit in same space defect rate gradually falls in time with same technology
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Current chip trends Increasing Area Yield – ( Increases / ------------) chance of a defect on die -> (-------- / Decreases ) yield Dies/wafer – ( -------- / fewer ) dies, ( more / ------ ) wasted space
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Example Current P4’s are 217mm 2 in 0.18-micron technology. A new 0.13-micron fab process should cut the die area in half. If
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This note was uploaded on 12/27/2011 for the course CMPSC 154 taught by Professor Franklin during the Fall '09 term at UCSB.

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Lec1BFabNotes - Fabrication Chapter 1, 2.19 Outline...

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