Lec10CacheExample

Lec10CacheExample - Caching Chapter 7 Memory Hierarchy CPU...

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Unformatted text preview: Caching Chapter 7 Memory Hierarchy CPU L1 L2 Cache DRAM Speed Fastest Slowest Size Smallest Largest Cost/bit Highest Lowest Tech SRAM (logic) SRAM (logic) DRAM (capacitors) 00 01 10 11 Direct-Mapped Cache Data Tag Valid 0x 10 10 01 Tag Index Byte Offset Block Offset Example 1 Direct-Mapped Block size=2 words 00 01 10 11 Direct-Mapped Cache Data Tag Valid Reference Stream: Hit/Miss 0b1001000 0b0010100 0b0111000 0b0010000 0b0010100 0b0100100 Miss Rate: Tag Index Byte Offset Block Offset Example 1 Direct-Mapped Block size=2 words Example 1 Direct-Mapped Block size=2 words 00 01 10 11 Direct-Mapped Cache Data Tag Valid Reference Stream: Hit/Miss 0b 10 01 00 0b0010100 0b0111000 0b0010000 0b0010100 0b0100100 Miss Rate: Tag Index Byte Offset Block Offset Example 1 Direct-Mapped Block size=2 words 00 10 01 10 11 M[76-79] Direct-Mapped Cache Data Tag Valid 1 Reference Stream: Hit/Miss 0b 10 01 00 M 0b0010100 0b0111000 0b0010000 0b0010100 0b0100100 Miss Rate: Tag Index Byte Offset Block Offset M[72-75] 00 10 01 10 11 Direct-Mapped Cache Data Tag Valid 1 Reference Stream: Hit/Miss 0b1001000 M 0b 00 10 1 00 0b0111000 0b0010000 0b0010100 0b0100100 Miss Rate: Tag Index Byte Offset Block Offset Example 1 Direct-Mapped Block size=2 words M[76-79] M[72-75] 00 10 01 00...
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This note was uploaded on 12/27/2011 for the course CMPSC 154 taught by Professor Franklin during the Fall '09 term at UCSB.

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Lec10CacheExample - Caching Chapter 7 Memory Hierarchy CPU...

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