Lec12n13 - Pipelining 6.1 6.2 Performance Measurements...

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Pipelining 6.1, 6.2
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Performance Measurements Cycle Time: Time __________________ Latency: Time to finish a _____________, start to finish Throughput: Average ______________ per unit time CyclesPerJob: On average, number of _______________________________.
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Goals Faster clock rate Use machine more efficiently No longer execute only one instruction at a time
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Laundry Laundry-o-matic washes, dries & folds Wash : 30 min Dry : 40 min Fold : 20 min It switches them internally with no delay How long to complete 1 load? ______
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Laundry-o-Matic - SingleCycle Minutes Load 1 2 3 0 30 60 90 120 150 180 210 240 270 W F D
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Laundry-o-Matic Cycle Time: Clothing is switched every ____ minutes Latency: A single load takes a total of ______ minutes Throughput: A load completes each ______ minutes CyclesPer Load : Every ____ cycle(s), a load completes
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Pipelined Laundry Split the laundry-o-matic into a washer, dryer, and folder (what a concept) Moving the laundry from one to another takes 6 minutes
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Pipelined Laundry Minutes Load 1 2 3 0 30 60 90 120 150 180 210 240 270 W F Switch all loads at the same time D
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Pipelined Laundry Cycle Time: Clothing is switched every ____ minutes Latency: A single load takes a total of ______ minutes Throughput: A load completes each ______ minutes CyclesPer Load : Every ____ cycle(s), a load completes
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Single-Cycle vs Pipelined _________ has the higher cycle time _________ has the higher clock rate _________ has the higher single-load latency _________ has the higher throughput _________ has the higher CPL (Cycles per Load ) More stages makes a _______ clock rate
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Obstacles to speedup in Pipelining W F D 1. 2. Ideal cycle time w/out above limitations with n stage pipeline:
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Creating Stages Fetch – get instruction Decode – read registers Execute – use ALU Memory – access memory WriteBack – write registers Fetch Decode Execute Memory WriteBack IF WB MEM ID
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Pipelined Machine src1 src1data src2 src2data Register File destreg destdata Addr Out Data Data Memory In Data 32 Sign Ext 16 << 2 Fetch (Writeback) Execute Decode Memory
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In what cycle was $s1 written? In what cycle was $s4 read? In what cycle was the Add executed? Time-> add $s0, $0, $0 lw $s1, 0($t0) sw $s2, 0($t1) or $s3, $s4, $t3 IF ID IF ID IF MEM ID IF 1 2 3 4 5 6 7 8 ID WB MEM WB MEM WB MEM WB
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Performance Analysis Measurements related to our machine Job = single instruction Latency - Time to finish a complete _______________, start to finish. Throughput – Average ______________ completed per unit time. CyclesPerInstruction – An _________ completes each how many cycles? Which is more important for reducing program execution time?
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Machine Comparison FetchDecode Execute Memory WriteBack 2ns 1ns 2ns 2ns 1ns 0.1 ns pipeline register delay Single-Cycle Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns Pipelined Implementation Clock cycle time: _____ ns Latency of a single instruction: _____ ns Throughput for machine: _____ inst/ns
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Example 2 – How do we speed up pipelined machine?
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This note was uploaded on 12/27/2011 for the course CMPSC 154 taught by Professor Franklin during the Fall '09 term at UCSB.

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Lec12n13 - Pipelining 6.1 6.2 Performance Measurements...

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