Parallel1

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Parallel Processing
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Problem: Branches, cache misses, dependencies limit the ILP available Solution:
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Motivations Desktops are incredibly cheap Squeezing out more ILP is difficult More software is multi-threaded
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Challenge Parallelizing code is not easy Communication can be costly
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Speedup _____________________ 70% of the program is parallelizable What is the highest speedup possible? What is the speedup with 100 processors?
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Taxonomy SISD – single instruction, single data SIMD – single instruction, multiple data MISD – multiple instruction, single data MIMD – multiple instruction, multiple data
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P Controller SIMD D P D P D P D P D P D P D P D Controller fetches instructions All processors execute the same instruction Conditional instructions only way for variation
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Example Sum the elements in A[] and place result in sum int sum=0; int i; for(i=0;i<n;i++) sum = sum + A[i];
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Parallel version Shared Memory
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Why can’t you figure out when proc x will
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This note was uploaded on 12/27/2011 for the course CMPSC 154 taught by Professor Franklin during the Fall '09 term at UCSB.

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Parallel1 - Parallel Processing Problem Branches cache...

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