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cs240a-matmul - CS 240A Matrix multiplication Matrix...

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CS 240A : Matrix multiplication Matrix multiplication I : parallel issues Matrix multiplication II: cache issues Thanks to Jim Demmel and Kathy Yelick (UCB) for some of these slides
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Matrix-Matrix Multiplication {implements C = C + A*B} for i = 1 to n for j = 1 to n for k = 1 to n C(i,j) = C(i,j) + A(i,k) * B(k,j) = + * C(i,j) C(i,j) A(i,:) B(:,j) Algorithm has 2*n3 = O(n3) Flops and operates on 3*n2 words of memory
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Communication volume model Network of p processors Each with local memory Message-passing Communication volume ( v ) Total size (words) of all messages passed during computation Broadcasting one word costs volume p (actually, p-1 ) No explicit accounting for communication time Thus, can’t really model parallel efficiency or speedup; for that, we’d use the latency-bandwidth model
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Parallel Matrix Multiply Compute C = C + A*B Basic sequential algorithm: C(i,j) += A(i,1)*B(1,j) + A(i,2)*B(1,j) +…+ A(i,n)*B(n,j) work = t 1 = 2n 3 floating point operations (“flops”) Variables are: Data layout Structure of communication Schedule of communication
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Matrix Multiply with 1D Column Layout Assume matrices are n x n and n is divisible by p A(i) is the n-by-n/p block column that processor i owns (similarly B(i) and C(i)) B(i,j) is the n/p-by-n/p sublock of B(i) in rows j*n/p through (j+1)*n/p Formula: C(i) = C(i) + A*B(i) = C(i) + Σ j=0:p-1 A(j) * B(j,i) p0 p1 p2 p3 p5 p4 p6 p7 (A reasonable assumption for analysis, not for code)
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Matmul for 1D layout on a Processor Ring Proc k communicates only with procs k-1 and k+1 Different pairs of processors can communicate simultaneously Round-Robin “Merry-Go-Round” algorithm Copy A(myproc) into MGR (MGR = “Merry-Go-Round”) C(myproc) = C(myproc) + MGR*B(myproc , myproc) for j = 1 to p-1 send MGR to processor myproc+1 mod p (but see deadlock below) receive MGR from processor myproc-1 mod p (but see below) C(myproc) = C(myproc) + MGR * B( myproc-j mod p , myproc) Avoiding deadlock: even procs send then recv, odd procs recv then send or, use nonblocking sends Comm volume of one inner loop iteration = n 2
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Matmul for 1D layout on a Processor Ring One iteration: v = n2 All p-1 iterations: v = (p-1) * n2 ~ pn2 Optimal for 1D data layout: Perfect speedup for arithmetic A(myproc) must meet each C(myproc) “Nice” communication pattern – can probably overlap independent communications in the ring. In latency/bandwidth model (see extra slides), parallel efficiency e = 1 - O(p/n)
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MatMul with 2D Layout Consider processors in 2D grid (physical or logical) Processors can communicate with 4 nearest neighbors Alternative pattern: broadcast along rows and columns Assume p is square s x s grid p(0,0) p(0,1) p(0,2) p(1,0) p(1,1) p(1,2) p(2,0) p(2,1) p(2,2) p(0,0) p(0,1) p(0,2) p(1,0) p(1,1) p(1,2) p(2,0) p(2,1) p(2,2) p(0,0) p(0,1) p(0,2) p(1,0) p(1,1) p(1,2) p(2,0) p(2,1) p(2,2) = *
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Cannon’s Algorithm: 2-D merry-go-round … C(i,j) = C(i,j) + Σ A(i,k)*B(k,j) assume s = sqrt(p) is an integer forall i=0 to s-1 “skew” A left-circular-shift row i of A by i … so that A(i,j) overwritten by A(i,(j+i)mod s) forall
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