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Intel48core - Single-chip Cloud Computer An experimental...

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Jim Held Intel Fellow & Director Tera-scale Computing Research “Single - chip Cloud Computer” An experimental many-core processor from Intel Labs Intel Labs Single-chip Cloud Computer Symposium February 12, 2010
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Agenda 10:00 Welcome and Opening Remarks 10:15 SCC Hardware Architecture Overview 11:15 Today’s SCC Software Environment 12:15 Buffet Lunch Informal discussions 13:15 Message Passing on the SCC 13:45 Software-Managed Coherency 14:15 Application ”Deep Dive”: Javascript Farm on SCC 14:45 Break 15:00 Plans for future SCC access 15:30 Q&A 16:30 Adjourn 2
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Motivations for SCC Many-core processor research High-performance power-efficient fabric Fine-grain power management Message-based programming support Parallel Programming research Better support for scale-out model servers > Operating system, communication architecture Scale-out programming model for client > Programming languages, runtimes 3
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Agenda 10:00 Welcome and Opening Remarks 10:15 SCC Hardware Architecture Overview 11:15 Today’s SCC Software Environment 12:15 Buffet Lunch Informal discussions 13:15 Message Passing on the SCC 13:45 Software-Managed Coherency 14:15 Application ”Deep Dive”: Javascript Farm on SCC 14:45 Break 15:00 Plans for future SCC access 15:30 Q&A 16:30 Adjourn 4
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Jason Howard Advanced Microprocessor Research Intel Labs SCC Architecture and Design Overview Intel Labs Single-chip Cloud Computer Symposium February 12, 2010
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Agenda Feature set Architecture overview Core Interconnect Fabric Memory model & Message passing I/O and System Overview Design Overview Tiled design methodology Clocking Power management Results Summary 6
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SCC Feature set First Si with 48 iA cores on a single die Power envelope 125W Core @1GHz, Mesh @2GHz Message passing architecture > No coherent shared memory > Proof of Concept for scalable solution for many core Next generation 2D mesh interconnect > Bisection B/W 1.5Tb/s to 2Tb/s, avg. power 6W to 12W Fine grain dynamic power management > Off-die VRs 7
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MC0 MC1 MC2 MC3 System Interface VRC Router IA-32 Core0 L2$0 256KB L2$1 256KB IA-32 Core1 MPB 16KB Router Tile Die Architecture 2 core clusters in 6x4 2-D mesh 16B 8
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Core Memory Management Core cache coherency is restricted to private memory space Maintaining cache coherency for shared memory space is under software control Each core has an address Look Up Table (LUT) extension Provides address translation and routing information LUT must fit within the core and memory controller constraints LUT boundaries are dynamically programmed Shared Boot 1GB Private Maps to MC0 Maps to VRC Maps to MPBs Maps to MC0 CORE0 LUT Example 0 1 254 255 9
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On-Die 2D Mesh 16B wide data links + 2B sideband > Target frequency: 2GHz > Bisection bandwidth: 2 Tb/s > Latency: 4 cycles (2ns) 2 message classes and 8 VCs Low power circuit techniques > Sleep, clock gating, voltage control, low power RF > Low power 5 port crossbar design Speculative VC allocation Route pre-computation Single cycle switch allocation 10
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