reverse-vietor

reverse-vietor - Reversible Computing Architectural...

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Reversible Computing Architectural implementation using only reversible primitives Perform logical operations in a reversible manner May be used to implement classical logic Able to write compilers that would run normal code Could allow for scaling of classical logic
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Circuit Level Requirements Not destroy information Inputs must be derivable by examining outputs Balanced number of inputs and outputs Use a physical process which allows operation in whichever direction driving force is applied System must by physically reversible in addition to logically reversible They are equivalent
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Why bother with reversibility? Process improvements are eventually a dead end Energy usage will become prohibitive Heat dissipation will become more problematic Classical computer dissipates a lot of energy Bulk electron processes Many electrons used to do a single logical operation
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Current Energy Usage Current Energy Dissipation Consider an average desktop processor 2 x 10^9 Hz Clock speed, 5 x 10^7 Logical Elements, 100 watts, 1.65 volts 10^-12 Joules/Logical operation Power density 1 cm^2 die size Assume 100 um thickness 10 Watts / mm^3
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Does Not Scale Does not scale in the long term. Target system 10^10 Hz Clock 10^17 Logical elements Very ambitious Classical architecture is not dead yet Current tech 10^15 watts Average Energy generation for 2004 in the USA 5 x 10^11 watts
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This note was uploaded on 12/27/2011 for the course CMPSC 290h taught by Professor Chong during the Fall '09 term at UCSB.

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reverse-vietor - Reversible Computing Architectural...

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