08-MonolithicInductance - EE 541 Fall 2009 Course Notes#8...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 541, Fall 2009: Course Notes #8 The Modeling Of The Monolithic Inductance Dr. John Choma Professor of Electrical Engineering University of Southern California Ming Hsieh Department of Electrical Engineering University Park: Mail Code: 0271 Los Angeles, California 90089–0271 213–740–4692 [USC Office] 213–740–8677 [USC Fax] [email protected] ABSTRACT: The realization of high quality monolithic inductances, as might be used in oscillators, filters, and compensation elements in broadband amplifiers, is a daunting task because the relatively large surface area required of reasonably valued inductances incurs numerous parasitic effects that degrade their high frequency electrical characteristics. A model accounting for most of these degrading influences is developed and analyzed. The primary fruits of this analysis are the formulation of a general small signal model of a monolithic inductance and the deduction of the frequency response of the inductor quality factor in terms of designable inductance value and relevant geometric parameters. Original: July 2006
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Course Notes #7 USC Viterbi School of Engineering John Choma 1.0. SPIRAL INDUCTANCES The most commonly adopted monolithic inductance is the square spiral depicted in Fig- ure (1). The indicated spiral is comprised of n turns of metallization traces, each uniformly sepa- rated by dimension s m and each having width, w m . The overall structure has an outer surface diameter of d o , an inner diameter of d i , and an overall length, l . Several layers of metallization are required to realize a good quality inductor of inductance value L s . The indicated top metal winding of this structure is invariably the topmost chip metal layer for two reasons. First, top- most metal layers tend to be thicker than lower level metal layers, thereby resulting in smaller resistances in the individual lengths of the spiral traces, and thus a smaller net series resistance associated with the realized inductance. In cases where small winding resistance is of paramount importance, several higher-level metal layers can be strapped together to forge effectively thicker winding metallization and therefore reduced series resistance. Second, the topmost metal layer is the furthest from the semiconductor substrate. Since the capacitance between a metal layer and a semi-conductive substrate is inversely proportional to the intervening distance between the layer and the substrate, a top layer metal winding delivers minimal net capacitance from spiral metal - to- ground. Although Figure (1) depicts only a square spiral geometry, which subscribes to com- monly invoked Manhattan circuit layout rules, circular, hexagonal, and octagonal spiral layouts are possible in the state of the art. These alternative structures serve to reduce, albeit minimally, the net series resistance of the ultimately realized inductance. However, for given inner and outer diameter dimensions, circular, hexagonal, and octagonal spiral inductors deliver smaller inductance values than do more traditional square spirals.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 12/22/2011 for the course EE 541 at USC.

Page1 / 20

08-MonolithicInductance - EE 541 Fall 2009 Course Notes#8...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online