{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

ee541F10HWSolutions07

ee541F10HWSolutions07 - U niversity of S outhern C...

This preview shows pages 1–4. Sign up to view the full content.

U niversity of S outhern C alifornia USC Viterbi School of Engineering Ming Hsieh Department of Electrical Engineering EE 541: Solutions, Homework #07 Fall, 2010 Due: 11/16/2010 Choma Solutions Problem #31: A particular type of multi-loop feedback amplifier is designed to deliver a driving point input impedance, Z in (s) , that is identical to the Thévenin equivalent resistance, R , of the signal source, V s . Although the design achieves Z in (s) = R at low signal frequencies, the input impedance degrades at high signal frequencies in accordance with the model shown in Figure (P31a). Note therein that Z in (s) matches the signal source resistance at low frequencies but de- grades toward zero at high frequencies. Compensate for this input impedance response by intro- ducing an appropriate impedance, Z(s) , in series with the signal source and the input port, as suggested in Figure (P31b). It is to be understood that the objective of Z(s) is to ensure that the indicated impedance, Z t (s) , is identical to R for all signal frequencies. The Z(s) adopted for this compensation scheme should exploit interconnections of only passive, lumped elements. Show a schematic diagram of Z(s) , with all element values thereof expressed in terms of model resis- tances R 1 and R and capacitances C 1 and C 2 . R 1 Z (s) in R C 2 V i C 1 R V s + (a). R 1 Z (s) in R C 2 V i C 1 R V s + (b). Z(s) Z (s) t V t Figure (P31) (a). Design the network shown in Figure (P31b) if R = 50 Ω , C 1 = 20 fF , C 2 = 3 fF , and R 1 = 75 . The natural candidate for the required impedance, Z(s) , can be found in the Class Lecture Aids. In particular, the compensation takes on the form shown in Figure (P31.1). In this diagram, () 1 21 11 b 2 12 1 1 1 1 2 1 R sC sC 1 sRC 1 Z . sC sC 1 sR C sC sC s R C C R sC sC ⎛⎞ + ⎜⎟ ++ ⎝⎠ == = (P31-1) Since constant input resistance at the input port requires Z a Z b = R 2 ,

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
EE 541 University of Southern California Viterbi School of Engineering Choma () 2 12 1 1 2 a2 1 11 22 1 Rs C s C1 s R C 1 Z sR C , R1 1s R C R sR C ++ ⎡⎤ ⎣⎦ == + + + (P31-2) R 1 R R C 2 C 1 R V s + Z a Z( s ) in V i Z(s) t V t Z b Z(s) Figure (P31.1) which suggests that an inductor of value R 2 C 2 be placed in series with the shunt interconnection of a resistance of value R 2 /R 1 and an inductance of value R 2 C 1 . The resultant compensated network appears in Figure (P31.2), where R 2 C 2 = 7.50 pH , R 2 /R 1 = 33.33 Ω , R = 50 , and R 2 C 1 = 50 pH . R 1 R R R/R 2 1 C 2 C 1 R V s + Z (s) in V i t V t Z(s) RC 2 2 2 1 Figure (P31.2) -20 0 20 40 60 1 10 100 Compensated Real Part Input Impedance Uncompensated Real Part Input Impedance Uncompensated Imaginary Part Input Impedance Compensated Imaginary Part Input Impedance Signal Frequency (GHz) Input Impedance ( ) Figure (P31.3) Solutions, Homework #07 82 Fall Semester, 2010
EE 541 University of Southern California Viterbi School of Engineering Choma Solutions, Homework #07 83 Fall Semester, 2010 (b).

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 12

ee541F10HWSolutions07 - U niversity of S outhern C...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online