EE577

EE577 - University University of Southern California...

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University of Southern California Viterbi School of Engineering EE577B LSI System Design VLSI System Design lock and Power Distribution Clock and Power Distribution Reference: Professor Pedram’s Notes Shahin Nazarian Fall 2010
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Motivation So far (in EE477L, EE577A and even in EE577B) our focus has been on 1) designing logic logic cells and arranging them gether to build sequential and combinational elements such together to build sequential and combinational elements such as memories and ALUs; and also 2) syndicating combinational and sequential parts to create a desired system Example: The DDR2 controller that consists of several sequential and combinational units However, a major design step in real industrial setting is the design of the ____ and ______ distribution networks. This in fact takes most of the design time, because the rest (logic cells and FFs) are already predesigned, verified nd added to the library. All we need to do is to instantiate Shahin Nazarian/EE577B/Fall 2010 and added to the library. All we need to do is to instantiate and connect them 2
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Motivation (Cont.) In parallel, the existing ASIC design flow tools and methodologies are mainly on supporting ASIC design, static timing analysis, automated gate sizing and replacement, and also buffering and sizing of wires to chieve a speed target while minimizing the power achieve a speed target while minimizing the power dissipation herefore what specifically changes from one design to Therefore what specifically changes from one design to another is on how ______ is distributed and how is delivered to where it is needed while meeting ______ is delivered to where it is needed while meeting a certain level of ____ in the clock and power distribution network Shahin Nazarian/EE577B/Fall 2010 3
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Outline Definitions Issues Solutions ostly on designing the of the power and Mostly on designing the ________ of the power and clock ____________ network and effective buffering to meet SI requirements _______ techniques such as clock deskewing which uses a feedback control loop to dynamically manage the spread of clock skew/jitter in the circuit Shahin Nazarian/EE577B/Fall 2010 4
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Digital System Classification based on Timing Synchronous systems operate off of a triggering edge of a clock or set of clocks (our discussion applies to these types of systems) synchronous ystems do not have any specific clocks Instead Asynchronous systems do not have any specific clocks. Instead they use a _______ protocol btn the sender and receiver blocks to manage timing synchronization. They have a tradeoff between the amount of _________ timing assumptions and the performance of the asynchronous pipeline. The faster the design, the more assumptions it has to embed. The performance of a truly time independent asynchronous design is not high Shahin Nazarian/EE577B/Fall 2010 5
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Timing Constraints For a synchronous design, within the clock period and subject to clock skew and jitter, we should consider the ___-to-__ ropagation delay of the input FF and also the me
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EE577 - University University of Southern California...

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