DDR2 Phase2_1

DDR2 Phase2_1 - EE577b DDR II Project EE577b DDR II Project...

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Unformatted text preview: EE577b DDR II Project EE577b DDR II Project phase2 phase2 Friday Oct 22 2010 M.Ghasemazar Project Phase 2 Project Phase 2 c Due: Wed 10/27 by 11:59PM (RTL) c You are allowed to work in groups of up to two students and turn in one bmission. submission. c Students have full freedom to improve the design to achieve higher data bandwidth. c No report is required now. c Design, Test, and Synthesis. DDR2 SDRAM Memory Controller DDR2 SDRAM Memory Controller overview overview t Address space management Memory bank interleaving t DDR2 Initialization Design and synthesis issue t FIFO Buffers t DDR2 Read and Write Timing robe alignment during write Strobe alignment during write Strobe alignment during read t Memory transactions processor Write Read c Buffer allocation for return data Bank Management t Refresh controller t Testbench Data format DDR2 Controller overview DDR2 Controller overview Models the requests from CPU/SRAM DDR2 Module Your design Interface DDR2 Controller overview DDR2 Controller overview c Part I: initialization phase c Part II: alar read scalar read scalar write bank interleaving Scalar operations...
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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DDR2 Phase2_1 - EE577b DDR II Project EE577b DDR II Project...

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