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DDR2 Phase2_1

DDR2 Phase2_1 - EE577b EE577b DDR II Project phase2 Friday...

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EE577b DDR II Project phase2 Friday Oct 22 2010 M.Ghasemazar
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Project Phase 2 circle5 Due: Wed 10/27 by 11:59PM (RTL) circle5 You are allowed to work in groups of up to two students and turn in one submission. circle5 Students have full freedom to improve the design to achieve higher data bandwidth. circle5 No report is required now. circle5 Design, Test, and Synthesis.
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DDR2 SDRAM Memory Controller overview triangle45right Address space management Memory bank interleaving triangle45right DDR2 Initialization Design and synthesis issue triangle45right FIFO Buffers triangle45right DDR2 Read and Write Timing Strobe alignment during write Strobe alignment during read triangle45right Memory transactions processor Write Read circle3 Buffer allocation for return data Bank Management triangle45right Refresh controller triangle45right Testbench Data format
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DDR2 Controller overview Your Models the requests from CPU/SRAM DDR2 Module design Interface
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DDR2 Controller overview circle5 Part I: initialization phase circle5 Part II: scalar read scalar write bank interleaving
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Scalar operations circle5 Scalar Read (SCR): with a SCR command, a 25-bit address is given to the controller at the ADDR[24:0] port. A single 16-bit
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