DDR2_overview_update

DDR2_overview_update - DDR2 Project Overview Ko Chung Tseng...

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Unformatted text preview: DDR2 Project Overview Ko Chung Tseng Outlines Why does DDR2 memory need a controller? What functions should the controller have? Read the data sheet? (>100 Pages.) Some terms: BL, CL, AL, RL, WL, Mode Registers How to initialize DDR2 memory? Bank Interleaving Outlines Why does DDR2 memory need a controller? What functions should the controller have? Read the data sheet? (>100 Pages.) Some terms: BL, CL, AL, RL, WL, Mode Registers How to initialize DDR2 memory? Bank Interleaving Why does DDR2 memory need a controller? To operate the DDR2 memory correctly, we need to design a controller which can assert commands/written in data (for write operations) as well as receive the read out data (for read operations) at the right time. See how many timing diagrams we have in the datasheet. Timing, Timing, Timing !!! Aside State machine(s) plus counter(s) will do. Read operation as an example. (Fig 37) Make the controller assert ACTIVE and READ at T0 and T1, respectively. At T6, your controller could latch the data delivered from DDR2 memory. Outlines Why does DDR2 memory need a controller? What functions should the controller have? Read the data sheet? (>100 Pages.) Some terms: BL, CL, AL, RL, WL, Mode Registers How to initialize DDR2 memory? Bank Interleaving DDR2 Project Overview How does DDR2 work? Please read the data sheet. Your design Model the requests from CPU/SRAM Interface What functions inside? How does DDR2 work? Please read the data sheet. Your design Model the requests from CPU/SRAM Interface Inside DDR2 Controller (Simplified Illustration) After initialization, the controller can work with DDR2 memory and perform READ/WRITE operations. For every 64 ms, the controller will issue commands to make the DDR2 memory itself. Each circle below may be a state machine. Outlines Why does DDR2 memory need a controller?...
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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DDR2_overview_update - DDR2 Project Overview Ko Chung Tseng...

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