DDR2_Phase1_2_update

DDR2_Phase1_2_update - DDR2ProjectPhase1(cont.)...

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DDR2 Project Phase1 (cont.) Ko Chung Tseng
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Announcement The corrections made in notes #6.1 and #6.2 You are allowed to work in groups of up to two students. We do NOT allow changing partners in the following project assignment. Choose your partner wisely in Project Phase #1. Any cheating in project will result in an F letter grade. Quiz will ask questions on DDR2 project. We will randomly pick students to give a presentation.
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Outline Review (DDR2 Project Overview) Controller (A Simplified Illustration) Controller (A More Detailed Illustration) Initialization Sample File (DDR2_init.tar) DDR2 controller module for Phase1 Submission
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Outline Review (DDR2 Project Overview) Controller (A Simplified Illustration) Controller (A More Detailed Illustration) Initialization Sample File (DDR2_init.tar) DDR2 controller module for Phase1 Submission
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DDR2 Project Overview How does DDR2 work? Please read the data sheet. Your design Model the requests from CPU/SRAM Interface
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What functions inside? How does DDR2 work? Please read the data sheet.
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DDR2_Phase1_2_update - DDR2ProjectPhase1(cont.)...

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