DDR2_Phase3

DDR2_Phase3 - DDR2ProjectPhase3 KoChungTseng Announcement...

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DDR2 Project Phase3 Ko Chung Tseng
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Announcement The testbench and SSTL cannot be changed. The test pattern for phase III can be used to test block operations and refresh logic. You may create your own input pattern to further test your controller design. No PrimeTime required. Any cheating in project will result in an F letter grade.
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Outline Burst type Phase III Block Read and Write Refresh Logic Submission
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Burst Type In initialization, you set “Burst Type” In the sample file, we used “sequential”.
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Burst Type (cont.) Assume the address of the first word always starts with Addr[2:0]=3’b000. Given “sequential” as your burst type, “SZ” is the number of banks you need to activate. Given “interleaved”, each read/write requires to activate multiple banks.
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In the sample file, we used “sequential”. The following slides will introduce phase III
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DDR2_Phase3 - DDR2ProjectPhase3 KoChungTseng Announcement...

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