Discussion_01

Discussion_01 - EE577B (08/28/2010) Outline - Examples:...

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EE577B (08/28/2010) Outline - Examples: Verilog Codes . A 1-bit adder design . A state machine design: An arbiter - Tool (for Pre-synthesis simulation) - To run Simulation . run.csh . makefile
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A combination logic design module adder1bit(A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; reg [1:0] SUM; reg S, Cout; always @ (A or B or Cin) begin SUM[1:0]=A + B + Cin; S = SUM[0]; Cout = SUM[1]; end endmodule // adder1bit `timescale 1ns/10ps module tb; wire S_out, C_out; reg A_in; reg B_in; reg C_in; adder1bit Adder(A_in,B_in,C_in,S_out,C_out); initial begin A_in=0; B_in=0; C_in=0; #10; A_in=1; B_in=0; C_in=0; #10; A_in=1; B_in=1; C_in=0; #10; A_in=1; B_in=1; C_in=1; end endmodule
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State machine
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An arbiter design (taken from http://www.asic-world.com/ ) To help you follow the tutorial, I have taken a simple arbiter as the example; this has got two request inputs and two grant outputs, as shown in the signal diagram below. When req_0 is asserted, gnt_0 is asserted When req_1 is asserted, gnt_1 is asserted When both req_0 and req_1 are asserted then gnt_0 is asserted i.e. higher priority is given to req_0 over req_1.
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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Discussion_01 - EE577B (08/28/2010) Outline - Examples:...

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