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EE577b_Lecture_01_&_02_082510

EE577b_Lecture_01_&_02_082510 - University of...

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Unformatted text preview: University of Southern California Viterbi School of Engineering EE577B VLSI System Design An Introduction to ASIC Design Reference: Main and recommended textbooks, online resources and Professor Pedram’s slides Shahin Nazarian - Fall 2010 Integrated Circuit Design Domains BehOVioral : Behavioral Domain — MRS)“ \BQ\{\Q\\X\' Q ( Systems Algorithms . Structural Domain Architectural Abstraction Operating Systems RTL Abstraction Processor. SOC Applications ,...--‘-—-——_t__‘ Hardware Modules Logic Abstraction Programs ______ Register Transfer Structural : Logic ALUs, Registers Subroutines Gates, Flip-Flops , Statements Instructions Transistors —Co~«\9 Wm g qfimw ' (3%de {o ‘M Circuit Abstraction Rectangles Physical : _ im\ mama WM: \33 ' Cd's CG“? 0 Mfi S& C§“M6¥ \C) ”)3 , Modules Chips Example: _ Boards, Systems Physical Domain Shahin Nazarian/ EE577B / Fall 2010 2 Design Abstraction Behavioral Domain Structural Domain Architectural Abstraction Domains can be hierarchically divided into different levels of LogicAbsflacfion W\$‘Q Ebb QR WC: \Q S! Register Transfer Program’s! ALUs. Registers namely 3:: S\(\‘ \\‘{C§W\QS§\ , L°9i° Subroutines Gates Flip-Flops &, m, and Statements Instructions Transistorg ‘ \tix abstractions Circuit Abstraction Rectangles Systems Operating Systems RTL Abstraction Processor. SOC Algorithms " Hardware Modules Applications ,.--'-—"“"*~—... '5 Cells ModjlleS// Chips Boards, Systems Physical Domain Shahin Nazarian / EE577B / Fall 2010 3 ! “With unit cost falling as the number of components per circuit rises, by 1975 economics may dictate squeezing as many as 65,000 components on a single silicon chip" from Gordon Moore's paper, April 19, 1965 Moore's paper: ftp : / / download . intel .com/ museum/ Moores_Law/ Articles - Press_Releases/Gordon_Moore_1 965_A rticle . pdf The number of transistors per $2 almost every \5 years As the number of transustors grows, _\_\_ SUV-5 Mt _ \‘G \om:\6\ Shahin Nazarian / EE577B / Fall 2010 4 CETR5\(International Technology Roadmap for Semiconductors) C \n ‘ [xi-Ellis LO» '3 No? “JV RAWWA N \ Water \\w M M‘ identifies the semiconductor technological challenges and needs over the next 15 years (www.itrs.net/ you may only look at the tables, to We most important information) The goal is to ensure vx 3:9 an to remove the roadblocks to the continuation of mock) {p500 Year Feature 2:04 2006 2008 2010 70 57 45 Technology node Clock GHz 4.17 6.78 10.97 MPU transistors 106/chip 193 307 487 DRAM size* Gbitlchip 1.0 MPU power 109 * Production size cited; 32 Gbitlchip introduced in 2010 Shahin Nazarian/EE577B /Fall 2010 2004 edition 5 ITRS Prediction! Feature 2004 Technology node Clock GHz 4.17 MPU transistors 106/chip 193 DRAM size* Gbitlchip dd MPU power * Production size cited; 32 Gbitlchip introduced in 2010 2004 edition Year 2006 2008 70 57 6.78 10.97 307 487 1.0 109 2010 45 1.0 120 As a VLSI designer you should be aware of This roadmap, if you are not already, however "VQM m Ntdwdrqsw ; NWT) \fl’” (Amp fiMV) {$3. CAM}? ka Shahin Nazarian/EE577B /Fall 2010 Chip Design: to become more challenging! The transistors continue to get QNAM and £9)“; and the result is that the complex n ,, '39:; Caachips with bllllhn of transistors, get harder to design Transistors Per Die 1010. " 1965 Actual Data 16 2G 4G 109 - MOS Arrays 1 M08 Logic 1975 Actual Data 256M 512'“ 1915 Projegagn 54ml?” Itanium‘“ Pentium-3'4 Mem 16M , . , OW 4M 1/ Pentiumwm A Microprocessor 1M _ 1" _____- 256K i433}; 64K '386 TM 0235' 4K 15K '—' 0086 1“ r’sfiso/ 4004 1900 1965 1970 1975 1930 1985 1990 1995 2000 2005 2010 Shahin Naz arian/EE577B /Fall 2010 Our goal- in this course The main goal of this course is to learn the process of NNK ’ ‘ M... We won't assign you a project to design a billion transistor chip in this course however we make sure ~3¢Q"""" «.152. ‘ a} r‘f r \ fa. Even in industry you will not design a billion transistor chip s \w "— _I__ The design needs to be (find—(mm )Y‘o Deutle 5 EW ml». Abstraction hides Egg £55\ d3. 3,2333 5 $3: EPA m and N burden as results in o essentially it's analogofi ‘ in programming &\:§?\‘j Abstraction enables design Was well as 5,, WEI 9” (“j , and 59 ; MAE: Shghin Nazarian/EE577B /Fall 2010 8 Design Principles - Hierarchy Hierarchy or W5 breaking g Mggg flag“ Menuin RTL and then submodules To a lower M5 33 it ylevel (logic level) followed by flm‘lfigggl level mainly because This approach mm \SNU QGWCQRM \va \l\Q\\l{mipsQl\4l 20K)“ “Ml/l A controller alucontrol datapath standard bitslice zipper cell library ' I 000 inv4x flop ramslice l ' O O O fulladder or2 and2 mux4 RA \ nor2 inv nand2 mux2 l Shahin Nazarian/EE577B/Fall 2010 t“ Design Principles - Hierarchy (Cont) Example: A designer who works on an R‘l'L Tool is concerned aT The level of .CAQ'SE (i .e, \QQQSLV- “C(M‘QKQ. WNQKW, dWNW in“. Q MAE 5 m ) whereas when he/she looks aT The gaTe level, The _§>%‘?. CMAOA} lg (AW comes inTo play: There are also some sTaTisTical wire load models To use, buT The §deTfiETEEMEML is noT a concern. During E 23 m ,l design, however, This informaTion is required To be able To design a complex mulTi-GHz chip Shahin Nazarian / EE577B / Fall 2010 10 Design Principles - Regularity Regularity is to subdivide the design *3 CA “WWW? Qg ism x “mm m m - 5% Example: You built a one-bit adder. in EE477L and tried ._ W —-.-‘;\ 1. - if,“ “ -- "29”" “___”: but 'i not mg .51 " Note: Although infinitenumbr of gates exist (at least theoretically) ' I are *4“ Shahin Nazarian / EE577B / F all 2010 U 11 Design Principles - Modularity ..—-_—_——='|fi Modularity means designing modules with wk\\_ Mikzk gmgfisom m \kflfima 5“; lib fig] 330.“: @MNA r \r" As long as these modules have well- defined functions and I/O interfaces, you can dispotcfi tFIe des sign Shahin Nazarian / EE577B / F all 2010 12 Design Principles - ngiiiy Locality means to do computations \o CAN) , and avoid . Remembeffiflrfth—atT sailing is m (AV (“Wm (45an r F ‘ ” “MR‘ h \L‘) x m N\% \g @RWQ‘LQN" WW \vt \w to“, 013 (L. which means excessive delay (wire delay is a quadratithhction of the wire length) and power consumption Q.\l14 In HDL thIs means the _ (Uh E Van UL glib/A W: p “Maw By locality other than the specified extenal Interaces the module internals_ : “MW ’gfism “($va ”W Shahin Nazarian/EE577B / Fall 2010 13 Design Methodologies - Programmable FPGA (Field Programmable Gate Array) Fully fabricated - PLD (Programmable Logic Device) but with limited routing capability compared to ‘ CPLD (Complex PLD) ‘T ”4“"; val-Ev Fullucustom Semi—custom Programmable mm Ma skecl gate array CPLD Cell-based (MGM (CBIC) (standard cells) Shahin Nazarian / EE577B / Fall 2010 FPGA 18 Design Methodologies - Semi-Custom Gate array (GA) An example is a ASIC design Standard Cell -based ( ) which used To be common for Euflnléfi‘ éié'”."fi " Vania? FUll"CU5t°m Semi-custom Programmable Pug/R Ma aked gate array CPLD FPG A Cell-based (MGM (CBIC) (standard cells) Shahin Nazarian / EE577B / Fall 2010 ‘ 19 -cusl'om, because we still have - Standard Cells Custom Standard cell design is called 1'0 Sem .c 33 1 I1. 3— v1-._ .. mm... fig 35 w. x. .....w. a .aflfi‘fip‘? “FJuI. it‘s ‘i‘iifiilii‘dn .rl.‘ . .... ...... L. .... NOR3 . iflii’lln'dg 1... ....Hi/vr. «on hub Iu!‘ ...—1.. ..9"sflfli “HT ..Illfl Jug ._ slulsfi§g§s a. ._ avg; m NAND3 ‘. I am.“ 1H5”. figs"_wjfl“‘w:v NOR2 $§B 1:5: "figig’l. m... ...w afiasu. ”I1“ F‘ifiiflifliii‘llr “IVA. NAND2 k. .m s m. $1 y». d 0 nor "do?“ e cw mm. mm csn rr C/O' oo Alo ff I“ omomlzex UUMMWE Shahin Nazarian / EE577B / Fall 2010 Design Methodologies - Full-Custom The idea of semi-custom or programmable-based design is to pre- design some components and _ _ , however in full-custom the entire mask design A full—custom designer performs transistor sizing but standard cell -based designer FUH“CUSt°m Semi—custom Programmable IDLE/R Ma sked gate array CPLD FPGA Cell-based (MGA) (CBIC) (standard cells) Shahin Nazarian / EE577B / Fall 2010 21 Design Methodologies - Comparison As we go downward towards FPGA we lose and over and also over (reconfigurability in case of FPGA) Custom gives the performance, however the initial cost ( and hence capital expenditure) is the . This means it does not make sense to do custom if the demand is in the order of thousands of chips only! However if the demand is projected to be of chips, the company may choose , as the initial cost is paid off by the GbitslcmZ) ns) Die Area: 2.5x2.5 cm Voltage: 0.6 V Technology: 0.07 pm Density Max. Ave. Power Clock Rate (Mgates/cmZ) W/cmZ) (GHz * In single mask GA all steps except the final Gate Am” * - Single-Mask GA :5 clone maggmo&azanan/EE577B /Fall 2010 FPGA Methodology Comparison (Cont.) Question: The density of custom is 25/04 (about 60) times better than FPGA, however a lot of companies, such as Xilinx are in FPGA business why is that? Because The number of new designs per year is about 10000 or so: this number is going down, "A. of the new designs are going to be low volume, only 70 is going to be medium or high volume Die Area: 2.51125 cm Voltage: 0.6 V Technology: 0.07 pm ° Note the reduction of Gbits/cmZ in DRAM to ' __M901'e/sz In [Mgates/cmz) (W/cmz (GHz) cum“ deg-""5 swm. —-_-_ * In single mask GA all steps except the final Gate Array *—n— m mum is m single-Mum “-5-“ haifin flazarmn/ EE577B / F311 2010 ”GA ...
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