Synthesis Tutorial 2

Synthesis Tutorial 2 - EE577B Dr. Nazarian Fall 2010...

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Unformatted text preview: EE577B Dr. Nazarian Fall 2010 Synthesis Tutorial By: By: Mohammad Ghasemazar Friday Oct 8, 2010 Outline The Synthesis Process revisited Synthesizable/Non-synthesizable FSM Helpful Notes Homework #4 2 Synthesis Script - 1 # Setting variables for synthesis set design_name fsm ; set clk_period 5.0; set posedge 0.0; set negedge [expr $clk_period * 0.5]; # Reading source verilog file. # Copy your verilog file into ./src/ before synthesis. 3 read_verilog ./src/fsm.v ; # Setting $design_name as current working design. # Use this command before setting any constraints. current_design $design_name ; # If you have multiple instances of the same module, # use this so that DesignCompiler optimizea each instance separately uniquify ; # Linking your design into the cells in standard cell libraries. # This command checks whether your design can be compiled # with the target libraries specified in the .synopsys_dc.setup file. link ; Synthesis Script - 2 # Setting timing constraints for sequential logic. # => clock period, input delay, output delay # (1) Setting clock period. create_clock -name "clk" -period $clk_period -waveform [list $posedge $negedge] [get_ports clk]; # (2) Setting addtional constraints for clock signal, 4 # so that clock network should be ideal network without any buffers. set_dont_touch_network clk ; set_ideal_network clk ; # (3) Setting input path delays on input ports(except clock) relative to a clock edge . # Input signals will arrive after this delay. set_input_delay 1.0 -max -clock clk [remove_from_collection [all_inputs] [get_ports "clk"]] ; # (4) Setting output path delays on output ports relative to a clock edge....
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Synthesis Tutorial 2 - EE577B Dr. Nazarian Fall 2010...

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