Unit1_lecture-ASICDesign-Nazarian-EE577B-Fall10

Unit1_lecture-ASICDesign-Nazarian-EE577B-Fall10 -...

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University of Southern California Viterbi School of Engineering EE577B LSI System Design VLSI System Design n Introduction to ASIC Design An Introduction to ASIC Design Reference: Main and recommended textbooks, online resources and Professor Pedram’s slides Shahin Nazarian Fall 2010
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Integrated Circuit Design Domains Behavioral : _ Structural : _ Physical : _ xample: Shahin Nazarian/EE577B/Fall 2010 Example: _ 2
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Design Abstraction Domains can be hierarchically divided into different levels of _________________ , namely ___________ , _____, _______ , and _____________ abstractions Design flow includes a series of __ Shahin Nazarian/EE577B/Fall 2010 3
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Moore’s Law “With unit cost falling as the number of components per circuit rises, by 1975 economics may dictate squeezing as many as 65,000 components on a single silicon chip” from Gordon Moore’s paper, April 19, 1965 Moore’s paper: ftp://download.intel.com/museum/Moores_Law/Articles- ress Releases/Gordon Moore 965 Article pdf Press_Releases/Gordon_Moore_1965_Article.pdf The number of transistors per _________ almost every ___ years As the number of transistors grows, __ Shahin Nazarian/EE577B/Fall 2010 4
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ITRS (International Technology Roadmap for Semiconductors) The ITRS (_ ____) identifies the semiconductor technological challenges and needs over the next 15 years (www.itrs.net/ you may only look at the tables, to review some of the most important information) The goal is to ensure _____________________________________and to remove the roadblocks to the continuation of _____________ Feature Unit Year 2004 2006 2008 2010 Technology node nm 90 70 57 45 Clock GHz 4.17 6.78 10.97 15.08 MPU transistors 10 6 /chip 193 307 487 773 DRAM size* Gbit/chip 1 2 4 4 V dd V 1.2 1.1 1.0 1.0 PU 4 8 09 20 Shahin Nazarian/EE577B/Fall 2010 2004 edition MPU power W 84 98 109 120 * Production size cited; 32 Gbit/chip introduced in 2010 5
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ITRS Prediction! Feature Unit Year 2004 2006 2008 2010 echnology node m 0 0 7 5 Technology node nm 90 70 57 45 Clock GHz 4.17 6.78 10.97 15.08 MPU transistors 10 6 /chip 193 307 487 773 DRAM size* Gbit/chip 1 2 4 4 V dd V 1.2 1.1 1.0 1.0 PU power 4 8 09 20 2004 edition MPU power W 84 98 109 120 * Production size cited; 32 Gbit/chip introduced in 2010 As a VLSI designer you should be aware of this roadmap, if you are not already, however _____ Shahin Nazarian/EE577B/Fall 2010 6
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Chip Design: to become more challenging! The transistors continue to get ________ and ______ nd the result is that the complex chips and the result is that the complex _________ chips with ________ of transistors, get harder to design Shahin Nazarian/EE577B/Fall 2010 7
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Our goal in this course The main goal of this course is to learn the process of ______________________________________ e won’t assign you a project to design a billion transistor chip in We won t assign you a project to design a billion transistor chip in this course, however we make sure _____________________________________________________ __________ Even in industry you will not design a billion transistor chip ____________________________ The design needs to be _________________________________ Abstraction hides _________________________________ and results in ____________, so essentially it’s analogous to ________ in programming Shahin Nazarian/EE577B/Fall 2010 Abstraction enables design __________ as well as _______, _________, and __________ 8
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Design Principles – Hierarchy Hierarchy or _______________ is breaking _________________ in RTL and then submodules to a lower __________ level (logic vel) followed by level, mainly because this approach
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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Unit1_lecture-ASICDesign-Nazarian-EE577B-Fall10 -...

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