Unit2-Verilog-Nazarian-EE577B-Fall10_1

Unit2-Verilog-Nazarian-EE577B-Fall10_1 - University...

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University of Southern California Viterbi School of Engineering EE577B LSI System Design VLSI System Design troduction to Verilog Introduction to Verilog Shahin Nazarian Fall 2010
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ASIC Design Flow Shahin Nazarian/EE577B/Fall 2010 2
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ASIC Design Flow HDL provides us with a way to model different blocks From system specification to behavioral HDL is very crucial and has to be error-free If the system specification is not detailed enough, the HDL designer should resolve all the ambiguities with the spec writer (aka architectural designer or architect) Once the HDL is written it has to be verified, therefore some of the modules are not design modules, but modules to test that the chip works ith ystemC nd ystemVerilog architects Shahin Nazarian/EE577B/Fall 2010 3 With SystemC and SystemVerilog , architects themselves can model what they want to do, and that may even serve as the spec instead of English text
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Verilog and SystemVerilog History Verilog is an HDL that is used for specification, modeling and verification of electronic systems It was invented in 1983 at Gateway Design Automation (which was acquired by Cadence Design Systems in 1990). Cadence made Verilog an open standard in 1990 under OVI (Open Verilog International) Verilog became an IEEE standard in 1995 ( Verilog1995 or IEEE 1364-1995 ) and it had major updates in 2001 ( Verilog2001 or 1364- 2001 ) and minor updates in 2005 ( Verilog2005 or 1364-2005 ) SystemVerilog ( IEEE 1800-2005 ) is a superset of Verilog2005 which mainly adds high-level programming verification features to make it a combined HDL/HVL (Hardware Verification Language) In 2009, IEEE 1800-2005 standard was merged with the basic Verilog ( IEEE 1394-2005 ) standard, creating the IEEE Standard 1800-2009 Shahin Nazarian/EE577B/Fall 2010 Verilog-AMS , attempts to integrate analog and mixed signal modelling with traditional Verilog 4
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Verilog Abstraction If we had to write every transistor in Verilog, we could not build billion transistor chips herefore Verilog supports different levels of Therefore Verilog supports different levels of abstraction and models to manage the complexity of the design Behavioral Algorithm level Register transfer level Dataflow Structural Gate level Shahin Nazarian/EE577B/Fall 2010 Switch (transistor) level Combination of different levels 5
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Verilog Program Structure In Verilog, a digital system is described as a set of modules h f t h m d l h n t f t th Each of these modules may have an interface to other modules to define their interconnection Each module can be per file or multiple of them can be put in one file The modules may run concurrently, but usually we have one top level module which specifies a closed system containing both test data and hardware models The top level module invokes instances of other modules pm f m Modules can represent pieces of hardware ranging from simple gates to complete systems such as a processor Shahin Nazarian/EE577B/Fall 2010 6 Modules can either be specified behaviorally or structurally (or a combination of the two)
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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Unit2-Verilog-Nazarian-EE577B-Fall10_1 - University...

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