Unit3-StructuralVerilog-Nazarian-EE577B-Fall10_1

Unit3-StructuralVerilog-Nazarian-EE577B-Fall10_1 -...

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University of Southern California Viterbi School of Engineering EE577B LSI System Design VLSI System Design tructural Verilog Structural Verilog eferences: Main and recommended textbooks, and References: Main and recommended textbooks, and online resources Shahin Nazarian Fall 2010
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Structural Modeling Structural Verilog is useful when a synthesis tool is not accessible, or it has not synthesized a design that meets h c nstr ints th r f r s th d si n rs h v t the constraints, therefore we as the designers have to write a better implementation of some of the design omponents in structural level. Also structural design is components in structural level. Also structural design is useful for design components that are not synthesizable (e.g., a divider). Finally structural transistor level description of the cells in the library might be useful in LVS (layout vs schematic) although typically Spice format is used instead of the Verilog description LVS takes the netlist from post synthesis step and he layout from P&R step and compares them to Shahin Nazarian/EE577B/Fall 2010 the layout from P&R step and compares them to make sure they are logically equivalent 2
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Structural Modeling (Cont.) Structural Verilog can be looked at as the text description of the schematic (the netlist of some components from standard cell library) Structure can be described in Verilog using: Gate-level Modeling Built-in gate primitives User-defined primitives ransistor vel Modeling Transistor-level Modeling Switch-level primitives Shahin Nazarian/EE577B/Fall 2010 3
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Gate Level Modeling – Built-in Gate Primitives Multiple-input gates: and, nand, or, nor, xor, xnor Multiple-output gates: buf, not Tristate gates: bufif0, bufif1, notif0, notif1 ull gates: Pull gates pullup, pulldown Shahin Nazarian/EE577B/Fall 2010 4
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Gate Instantiation A gate can be used in a design using a gate instantiation (multiple instantiation is also possible) gate_type [instance_name1] (term11, term12,…,term1N), [instance_name2] (term21, term22,…,term2N), gate_type is one of the gate types listed on the previous page: and, or, xor, etc. instance_name is optional pecify nets and gisters (variables) Shahin Nazarian/EE577B/Fall 2010 terms spec fy nets and reg sters ( ar a les) connected to the terminals of the gates 5
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Multiple-input Gates Multiple-input built-in gates are: and, nand, nor, or, xor, xnor Syntax multiple_input_gate_type [instance_name] (output, input1, input2, …, inputN); First terminal is the output; all others are inputs Examples: or u1or (out, in1, in2); nand (out, i1, i2, i3, i4); xnor (out, d[1], d[2], d[3]), Shahin Nazarian/EE577B/Fall 2010 (xnor2o, intr_d[4], intr_d[5]); 6
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and/nand Truth Tables A z input is handled like an x Output can never be z and 0 1 x z nand 0 1 x z 0 0 0 0 0 1 01xx 0 1 1 1 1 1 10xx x 0 x x x z 0xxx x 1 x x x z 1xxx Tables for more than two inputs are similar and can be generated by the extrapolation of the tables bove Shahin Nazarian/EE577B/Fall 2010 above 7
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or/nor Truth Tables
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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Unit3-StructuralVerilog-Nazarian-EE577B-Fall10_1 -...

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