University of Southern CaliforniaViterbi School of EngineeringEE577BVLSI System DesignStructural VerilogReferences: Main and recommended textbooks, andReferences: Main and recommended textbooks, and online resourcesShahin Nazarian Fall 2010
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Structural Modeling•Structural Verilog is useful when a synthesis tool is not accessible, or it has not synthesized a design that meets th c nstr ints th r f r s th d si n rs h v t the constraints, therefore we as the designers have to write a better implementation of some of the design components in structural level. Also structural design is useful for design components that are not synthesizable (e.g., a divider). Finally structural transistor level description of the cells in the library might be useful in LVS (layout vs schematic) although typically Spice format i d itd f th Vildiptiis used instead of the Verilog description•LVS takes the netlist from post synthesis step and the layout from P&R step and compares them to Shahin Nazarian/EE577B/Fall 2010make sure they are logically equivalent2