Unit5-VerilogSynthesis-Nazarian-EE577B-Fall10

Unit5-VerilogSynthesis-Nazarian-EE577B-Fall10 - EE577B VLSI...

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EE577B VLSI System Design Verilog HDL Synthesis References: Main and recommended textbooks, and online resources Shahin Nazarian Fall 2010
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Shahin Nazarian/EE577B/Fall 2010 Overview It is important to know what we type as Verilog HDL is synthesizable or not and if so, what hardware it is going to infer. This helps avoid codes that result in (unwanted) latches Non-synthesizable design is useful for simulation and testbenches for debugging There are 3 main coding styles: behavioral, structural and dataflow; mixing them is fine as well. Behavioral RTL/Algorithmic is for large designs Structural style is typically used by machines rather than the designers Dataflow style is useful for small logic 2
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Shahin Nazarian/EE577B/Fall 2010 Synthesis Synthesis is the process of converting a high-level description of design into an optimized gate-level representation The designer should first understand and design the architectural description which is written in Hardware Description Language (HDL) such as Verilog. To do synthesis, the HDL code needs to be synthesizable, but more importantly a cell library (technology library) should also be available to the synthesis tool, so there has to be a way to implement the logic in the behavioral code Synthesis is complicated and multiple runs may not give the same result 3 Design constraints
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Shahin Nazarian/EE577B/Fall 2010 Synthesis (Cont.) The standard cell library (technology library) has simple cells, such as basic logic gates like and, or, and nor, or macro cells, such as adder, muxes, memory, and flip-flops In addition to the library and HDL, the designer should consider design constraints (measurements) such as timing, area, testability, and power; e.g., if only area matters, RCA would be chosen, but if speed is the main requirements, CLA is preferred Note that the Synthesis tool cannot work successfully for every constraints the designer sets. If the constraints are too tight, the tool may run for days and eventually produce nothing but _________ Examples of synthesis tools are Blast Create by Magma DA, BooleDozer by IBM, Design Compiler by Synopsys, Encounter RTL Compiler by Cadence, LeonardoSpectrum by Mentor Graphics, Synplify Pro (FPGA synthesis) by Synopsys 4
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Shahin Nazarian/EE577B/Fall 2010 Synthesis (Cont.) Synthesis makes it possible to design technology independent descriptions and reuse them. A well- written HDL code can be used in future technologies; synthesized with their corresponding cell libraries which are possibly more advanced and possibly with better synthesis tools It makes higher level descriptions possible, which reduces the possibility of any error introduced by the designer A note on analog blocks: In ASIC design flow analog blocks are designed independently and integrated with logic blocks during full chip integration 5
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Shahin Nazarian/EE577B/Fall 2010 [Optional] Industrial Tools Example: http://www.magma-da.com/products-solutions/
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This note was uploaded on 12/22/2011 for the course EE 577 at USC.

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Unit5-VerilogSynthesis-Nazarian-EE577B-Fall10 - EE577B VLSI...

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