2010-10-21-discussion-design-verification

2010-10-21-discussion-design-verification - Verification...

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Unformatted text preview: Verification Strategy for Large Designs 10/21/2010 Hsunwei Hsiung 1 Outline • Basic ideas • Inter-level problems • Verification strategy 2 General idea • Difficulty in verification of a large design – Astronomical numbers of possible combinations: Logic values, voltage levels, rise/fall times, skews, etc. – Difficult to debug • Hierarchical Design – Manageable implementation • Design efficiency, storage efficiency – Facilitate the verification process • Isolate and fix problems at each level before proceeding to higher levels of design • Narrow down the scope of problems at higher levels 3 Inter-level Problems • Potential problems when connecting multiple low level cells • Delay issues – Incorrect estimation of delay • Especially in cases where delays are not additive • Voltage compatibility – Output voltage of one stage incompatible with the input voltage of the next – Charge sharing • Connecting dynamic gates: Lots of issues 4 • Manchester carry chain • Gi=ai∙bi • Pi=ai+bi 5 Incorrect Delay Estimation Incorrect Delay Estimation • Simulation – Worst case: – Critical path delay does not increase linearly 6 ? delays: 1-stage delay:0.15ns 4-stage delay:0.79ns =1, ? =0, ? =1 2v 0v 4 4.25 4.5 ns 4.75 5 5.25 0.9v 5.5 5.75 ¡ ¡ 1 ¡ 4 Connecting Dynamic Gates • Dynamic INV with dynamic NOR • ? = ¡ + ?...
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2010-10-21-discussion-design-verification - Verification...

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