2010-11-09-and-11-sequential-circuit-timing-lectures

2010-11-09-and-11-sequential-circuit-timing-lectures - EE...

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E 577a: Sequential Circuits EE 577a: Sequential Circuits Week starting November 9, 2010
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Background and challenges emory elements/sequencing elements Memory elements/sequencing elements – Flipflops Flipflops and latches and latches A A flipflop flipflop is an edge is an edge-triggered memory element triggered memory element – New value applied at output at a clock edge New value applied at output at a clock edge A latch is a level A latch is a level-sensitive sensitive memory element memory element – New value/signal New value/signal is transmitted is transmitted to output when to output when the clock is transparent the clock is transparent Latch Latch-based pipelines based pipelines – More difficult to design and verify than FF More difficult to design and verify than FF-based designs based designs – Allows Allows time borrowing (1) Higher Higher performance performance (2) Higher Higher yield yield Latch Latch-based circuits used in full based circuits used in full-custom high custom high-speed circuits, especially speed circuits, especially in highly delay in highly delay-critical parts critical parts 3
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Time borrowing in latch Time borrowing in latch-based circuits based circuits L 1 L 4 L 7 C 0 L 2 L C 1 L 5 L L 8 L 3 clk clk 6 9 clk 0 1 0 10 20 clk clk Nominal delay for C 0 4 Positive latches (active Positive latches (active-high) high) Nominal delay for each block: T/2 Nominal delay for each block: T/2 = 10 = 10 (T: clk period (T: clk period)
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Time borrowing in latch Time borrowing in latch-based circuits based circuits L 1 L 4 L 7 C 0 L 2 L C 1 L 5 L L 8 L 3 clk clk 6 9 clk 0 1 0 10 20 clk clk ime borrowing (TB): pplies a new alue at an Nominal delay for C 0 5 Time borrowing (TB): Time borrowing (TB): C 0 applies a new applies a new value at an value at an input of input of C 1 after rising edge of rising edge of clk clk
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Time borrowing occurs at L 5 L 1 L 4 L 7 C 0 L 2 L C 1 L 5 L L 8 L 3 6 9 clk clk clk 0 1 0 10 20 clk clk Delay = 12 orst case nominal delay at output L f C f C = 12 = 12 6 Worst case nominal delay at output L 5 of C 0 12 May be intentional intentional TB TB (by design) or unintentional TB (by defects and/or variations)
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C 0 L 3 L 4 C 1 L 6 L 7 C 2 L 9 L 10 L 0 L 1 L 5 L 8 L 11 L 2 clk clk clk clk clk clk “pass” “fail” Apply earliest – at rising edge of clk With respect to the earliest – at rising edge of clk – All chips with time borrowing may seem to “fail” – But may actually “pass” 7 • Depending on delays of multi-segment paths in C 0 +C 1 or C 0 +C 1 +C 2
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C L 3 L 4 C L 6 L 7 C L 9 L 10 L 0 L 1 0 L 5 1 L 8 2 L 11 L 2 clk clk clk clk clk clk Apply earliest – at rising edge of clk Capture latest – at falling edge of clk – Call this r-f mode of operation 8 – Maximum allowable delay for a block Nominal delay = T/2; maximum allowable = T
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When to apply inputs & capture responses?
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2010-11-09-and-11-sequential-circuit-timing-lectures - EE...

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