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Unformatted text preview: EE-577a VLSI System Design
In-Class Exercise 1 (ICE 1)
1. Consider the following questions related to the meaning and computation of noise margin.
a. If a complementary inverter design has inadequate noise margin, then in what ways can
you change the design to improve noise margin? b. In high-speed circuit design, would you try to maximize noise margin? Alternatively,
would your goal be to ensure that the noise margin is greater than a given limit? Explain. c. Outline an approach for computing noise margin for a two-input NAND gate. 2. Consider the following questions related to rise and fall delays.
a. Why don’t we define rise time at a gate’s output as the time it takes for the voltage at the
output to rise from 0v to Vdd, but instead use the time from 0.1Vdd to 0.9 Vdd? b. Why do we define rise delay between an input of a gate to its output as the time elapsed
between when the voltage at the input crosses 0.5Vdd and when the voltage at its output
crosses 0.5Vdd? 3. Now consider a few quick questions about labs.
a. How does the delay of a gate depend on the load at its output? b. If you were asked to compute the delay of a gate, what load values would you use? 2 c. What are the advantages of drawing and simulating a transistor-level schematic version
of a gate’s design before undertaking its layout? d. What are the advantages of thoroughly simulating a single adder cell before using 64
copies of the cell to obtain a 64-bit ripple carry adder? 3 ...
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This note was uploaded on 12/22/2011 for the course EE 577A at USC.