cmosis_layout_tutorial

cmosis_layout_tutorial - A Tutorial on Using the Cadence...

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Unformatted text preview: A Tutorial on Using the Cadence Virtuoso Editor to create a CMOS Inverter with CMOSIS5 Technology Developed by Ted Obuchowicz VLSI/CAD Spet, Dept. of Electrical and Computer Engineering Concordia University Feb.23, 1998 Revised: May 2006 Revision History October 26, 2000: updated the procedure to fill out the Extractor form for Cadence 2000a. Sept. 5, 2003: updated procedure for using non-global power supply pins (VDD and VSS instead of global power supply pins (VDD! and VSS!) since the HSPICE netlister in Cadence 2002a no longer extracts the global pins leading to no dc path from node XXX to ground error messages. Consequently, any schematic which makes use of an extracted symbol view of a layout will have to make explicit connections to a power supply source and the VDD and VSS pins which will now appear in the symbol of the extracted layout. Sept. 27, 2004: updated procedure on page 16 for simulating an extracted view of a layout since the extracted keyword no longer appears by default in the Switch View List of the Setup -> Envi- ronment form. Users MUST ensure that extracted appears before schematic in the Switch View List or else the simulation of the extracted layout will fail. For Cadence 2003a, the Environment form appears as: May, 2006: updated tutorial to include color Postscript images. Updated images and text to reflect Cadence 2004a. ii 1 INTRODUCTION This tutorial is an introduction to the Layout Editor available from the Cadence design tools and the CMOSIS5 design kit from the Canadian Microelectronics Corporation (CMC). This tutorial is based on the current version of Cadence (2004a). The CMOSIS5 design kit is based on the Hewlett-Packard CMOS14TB process. This is a high-speed, high density 0.5 micron CMOS pro- cess which feature a 0.6 micron drawn gate length optimized for 3.3 V operation. The CMOS14TB process is a triple-metal, single poly CMOS process. I: USING THE VIRTUOSO LAYOUT EDITOR TO CREATE A PMOS TRANSISTOR This section will explore the use of the Virtuoso Layout editor. A p-type MOS transistor will be designed. A p-type MOSFET transistor is fabricated with the CMOS14TB process by crossing polysilicon and N-Island in a P-Substrate. 1-1: Start the Cadence tools by typing the following command from the UNIX prompt: % cmosis5 The main CIW (Command Interpreter Window) will appear. The next step is to create a new library to hold your work. The library created must be attached to a specific technology file, in this case the CMOSIS5 design kit from the Canadian Microelectronics Corporation. 1-2: To create a new library and attach it to the CMOSIS5 technology file select: File -> New -> Library . The New Library window will appear. In this window fill in the following: Name: mylib (or any other suitable name), Technology File: select the Attach to an existing techfile button....
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This note was uploaded on 12/27/2011 for the course EE 101 taught by Professor Mosolino during the Spring '11 term at Kings College.

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cmosis_layout_tutorial - A Tutorial on Using the Cadence...

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